公开(公告)号：US20240105682A1

公开(公告)日：2024-03-28

申请号：US18526016

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Chen-Hua Yu ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Yih Wang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528 ,  H10B12/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/5283 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H10B12/02 ,  H10B12/315 ,  H10B12/50 ,  H10N50/01 ,  H10N50/80 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.

公开(公告)号：US20240088078A1

公开(公告)日：2024-03-14

申请号：US18150034

申请日：2023-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Hao Tsai ,  Yih Wang ,  Wei-Ting Chen ,  Chuei-Tang Wang ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1437

Abstract: Packaged memory devices including memory devices hybrid bonded to logic devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first memory die including a first memory cell electrically coupled to a first word line; a second memory cell electrically coupled to the first word line; and a first interconnect structure electrically coupled to the first word line; a circuitry die including a second interconnect structure, a first conductive feature of the first interconnect structure being bonded to a second conductive feature of the second interconnect structure through metal-to-metal bonds; and a word line driver electrically coupled to the first word line between the first memory cell and the second memory cell, the word line driver being electrically coupled to the first word line through the first interconnect structure and the second interconnect structure.

公开(公告)号：US11386936B2

公开(公告)日：2022-07-12

申请号：US16925295

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hiroki Noguchi ,  Ku-Feng Lin ,  Yih Wang

IPC: G11C7/02 ,  G11C7/06

Abstract: A memory device for sensing memory cell in a memory array includes at least one first memory cell, a first sensing amplifier, a first multiplexer circuit, a plurality of first reference cells, and a controller. The first sensing amplifier is coupled to the at least one first memory cell. An output terminal of the first multiplexer circuit is coupled to the reference terminal of the first sensing amplifier. Each of the first reference cells is coupled to each input node of the first multiplexer circuit. The controller is coupled to a control terminal of the first multiplexer circuit. The first sensing amplifier comprises an output terminal and a reference terminal. The controller controls the first multiplexer circuit to select one of the first reference cells as a selected reference cell to couple to the reference terminal of the first sensing amplifier when each read operation to the at least one first memory cell is performed.

公开(公告)号：US11342341B2

公开(公告)日：2022-05-24

申请号：US17025563

申请日：2020-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Chien-Ying Chen ,  Chia-En Huang ,  Yih Wang

IPC: H01L27/112 ,  G06F30/392 ,  H01L23/528 ,  H01L23/522

Abstract: A method of generating an IC layout diagram includes positioning a first active region between second and third active regions, intersecting the first active region with first through fourth gate regions to define gate locations of first and second anti-fuse bits, aligning first and second conductive regions between the first and second active regions, thereby intersecting the first conductive region with the first gate region and the second conductive region with the fourth gate region, and aligning third and fourth conductive regions between the first and third active regions, thereby either intersecting the third and fourth conductive regions with the first and third gate regions, or intersecting the third and fourth conductive regions with the second and fourth gate regions. At least one of positioning or intersecting the first active region, or aligning the first and second or third and fourth conductive regions is executed by a processor.

公开(公告)号：US11257827B2

公开(公告)日：2022-02-22

申请号：US16729973

申请日：2019-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Wan-Hsueh Cheng ,  Yao-Jen Yang ,  Yih Wang

IPC: G11C17/00 ,  H01L27/112 ,  H01L23/528 ,  G06F30/392 ,  G11C17/18 ,  H01L23/522 ,  G11C17/16

Abstract: A structure includes a first data line and a first anti-fuse cell including first/second programming devices and first/second reading devices. The first programming device includes a first gate and first/second source/drain regions disposing on opposite sides of first gate. The second programming device includes a second gate separate from the first gate and coupled to a first word line and third/fourth source/drain regions disposing on opposite sides of second gate. The first reading device includes a third gate and fifth/sixth source/drain regions disposing on opposite sides of third gate. The second reading device includes a fourth gate and seventh/eighth source/drain regions disposing on opposite sides of fourth gate. The third/fourth gates are parts of the first continuous gate coupled to a second word line. The fifth/seventh source/drain regions are coupled to the second/fourth source/drain regions, respectively. The sixth/eighth source/drain regions are coupled to the first data line.

公开(公告)号：US11237834B2

公开(公告)日：2022-02-01

申请号：US16923107

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hiroki Noguchi ,  Yih Wang

IPC: G06F9/30 ,  G06F11/10

Abstract: A memory device includes a memory array with at least one memory macro, a flag, and a controller. The controller is coupled to the memory array. Each bit of data stored in the at least one memory macro is presented as a first bit type or a second bit type. The controller is configured to select one of a first situation mode and a second situation mode as a selected situation mode according to a first retention time of the first bit type and a second retention time of the second bit type. The first situation mode is that a number of bits with the first bit type in data is larger than a number of bit with the second bit type in data, and the second situation mode is that the number of bit with the first bit type in data is not larger than the number of bits with the second bit type in data. In a write operation of the at least one memory macro, the controller determines that an input data is meet the selected situation mode or not. In response to the input data is meet the selected situation mode, the controller disables the flag and writes the input data into the at least one memory macro. In response to the input data is not meet the selected situation mode, the controller enables the flag, inverts the input data, and writes an inverted input data into the at least one memory macro.

公开(公告)号：US20210272606A1

公开(公告)日：2021-09-02

申请号：US16925295

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hiroki Noguchi ,  Ku-Feng Lin ,  Yih Wang

IPC: G11C7/06

Abstract: A memory device for sensing memory cell in a memory array includes at least one first memory cell, a first sensing amplifier, a first multiplexer circuit, a plurality of first reference cells, and a controller. The first sensing amplifier is coupled to the at least one first memory cell. An output terminal of the first multiplexer circuit is coupled to the reference terminal of the first sensing amplifier. Each of the first reference cells is coupled to each input node of the first multiplexer circuit. The controller is coupled to a control terminal of the first multiplexer circuit. the first sensing amplifier comprises an output terminal and a reference terminal. The controller controls the first multiplexer circuit to select one of the first reference cells as a selected reference cell to couple to the reference terminal of the first sensing amplifier when each read operation to the at least one first memory cell is performed.

公开(公告)号：US20210082495A1

公开(公告)日：2021-03-18

申请号：US16572625

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-En Huang ,  Hidehiro Fujiwara ,  Jui-Che Tsai ,  Yen-Huei Chen ,  Yih Wang

IPC: G11C11/419 ,  G11C11/418 ,  G11C5/06 ,  H01L27/11

Abstract: An integrated circuit and an operating method thereof are provided. The integrated circuit includes memory cells, at least one first word line, second word lines, bit lines and write-assist bit lines. The at least one first word line is electrically connected to at least one row of the memory cells. The second word lines are electrically connected to other rows of the memory cells. Two bit lines are located between a column of the memory cells and two write-assist bit lines. The bit lines and the write-assist bit lines are configured to be electrically disconnected with each other when at least one of the memory cells electrically connected with the at least one first word line is configured to be written, and electrically connected with each other when at least one of the memory cells electrically connected to the second word lines is configured to be written.

公开(公告)号：US12063773B2

公开(公告)日：2024-08-13

申请号：US17589580

申请日：2022-01-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Wan-Hsueh Cheng ,  Yao-Jen Yang ,  Yih Wang

IPC: G11C17/00 ,  G06F30/392 ,  G11C17/16 ,  G11C17/18 ,  H01L23/522 ,  H01L23/528 ,  H10B20/20

CPC classification number: H10B20/20 ,  G06F30/392 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5226 ,  H01L23/528

Abstract: A semiconductor device includes first and second active areas, a first gate, a first conductive segment, a first via and a first continuous gate. The first and second active areas extend in a first direction. The first gate crosses over the first active area and the second active area. The first gate includes a first gate portion and a second gate portion electrically isolated from each other. The first conductive segment crosses over the first active area and the second active area. The first via is arranged above the first conductive segment. The first active area and the second active area are coupled through the first conductive segment to the first via. The first continuous gate is disposed between the first conductive segment and the first gate, and crossing over the first active area and the second active area.

公开(公告)号：US12002534B2

公开(公告)日：2024-06-04

申请号：US17842256

申请日：2022-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chenchen Jacob Wang ,  Yi-Ching Liu ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Yih Wang

IPC: G11C5/06 ,  H01L29/24 ,  H01L29/78 ,  H01L29/786 ,  H10B41/27 ,  H10B51/00 ,  H10B51/10 ,  H10B51/20

CPC classification number: G11C5/063 ,  H01L29/24 ,  H01L29/78391 ,  H01L29/7869 ,  H10B41/27 ,  H10B51/00 ,  H10B51/10 ,  H10B51/20

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material contacting a first word line; an oxide semiconductor (OS) layer contacting a source line and a bit line, the FE material being disposed between the OS layer and the first word line; a dielectric material contacting the FE material, the FE material being between the dielectric material and the first word line; an inter-metal dielectric (IMD) over the first word line; a first contact extending through the IMD to the first word line, the first contact being electrically coupled to the first word line; a second contact extending through the dielectric material and the FE material; and a first conductive line electrically coupling the first contact to the second contact.