公开(公告)号：US20240385367A1

公开(公告)日：2024-11-21

申请号：US18785578

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia

IPC: G02B6/12 ,  G02B6/136

Abstract: A method includes forming a first photonic die, which includes forming a first silicon waveguide, and forming a first nitride waveguide. The method further includes forming a first through-via extending into a first plurality of dielectric layers in the first photonic die, and bonding a second photonic die to the first photonic die. The second photonic die includes a second nitride waveguide. The first silicon waveguide is optically coupled to the second nitride waveguide through the first nitride waveguide. A second through-via extends into a second plurality of dielectric layers in the second photonic die.

公开(公告)号：US20240377662A1

公开(公告)日：2024-11-14

申请号：US18415092

申请日：2024-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Lee ,  Tien-Lin Shen ,  Wei-Heng Lin ,  Hsing-Kuo Hsia ,  Chen-Hua Yu

IPC: G02F1/025 ,  G02F1/015

Abstract: An optical device and methods of manufacturing such optical devices are presented. In embodiments the optical device is a tunable beam splitter which is made by forming a first dopant region over a substrate, the first dopant region comprising a first waveguide and a second waveguide, depositing a cladding material over the first waveguide and the second waveguide, and forming a second dopant region overlying the first waveguide and the second waveguide, wherein the forming the second dopant region comprises forming a first region extending over both the first waveguide and the second waveguide, the first region having a constant concentration of a first dopant.

公开(公告)号：US20240371726A1

公开(公告)日：2024-11-07

申请号：US18778763

申请日：2024-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Rong Chun ,  Kuo-Lung Pan ,  Pei-Hsuan Lee ,  Chien Ling Hwang ,  Yu-Chia Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC: H01L23/40 ,  H01L23/00

Abstract: In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.

公开(公告)号：US12136612B2

公开(公告)日：2024-11-05

申请号：US17657843

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Tin-Hao Kuo

IPC: H01L25/10 ,  H01L25/00 ,  H01L25/18

Abstract: A package includes a building block. The building block includes a device die, an interposer bonded with the device die, and a first encapsulant encapsulating the device die therein. The package further includes a second encapsulant encapsulating the building block therein, and an interconnect structure over the second encapsulant. The interconnect structure has redistribution lines electrically coupling to the device die. A power module is over the interconnect structure. The power module is electrically coupled to the building block through the interconnect structure.

公开(公告)号：US20240363590A1

公开(公告)日：2024-10-31

申请号：US18767207

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Hao Tsai ,  Chuei-Tang Wang

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L21/566 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2924/1434

Abstract: A method includes thinning a semiconductor substrate of a device die to reveal through-substrate vias that extend into the semiconductor substrate, and forming a first redistribution structure, which includes forming a first plurality of dielectric layers over the semiconductor substrate, and forming a first plurality of redistribution lines in the first plurality of dielectric layers. The first plurality of redistribution lines are electrically connected to the through-substrate vias. The method further includes placing a first memory die over the first redistribution structure, and forming a first plurality of metal posts over the first redistribution structure. The first plurality of metal posts are electrically connected to the first plurality of redistribution lines. The first memory die is encapsulated in a first encapsulant. A second plurality of redistribution lines are formed over, and electrically connected to, the first plurality of metal posts and the first memory die.

公开(公告)号：US20240363463A1

公开(公告)日：2024-10-31

申请号：US18766996

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Hao-Yi Tsai ,  Tin-Hao Kuo

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/3114 ,  H01L21/486 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/214 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18162 ,  H01L2924/19041

Abstract: A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.

公开(公告)号：US20240363366A1

公开(公告)日：2024-10-31

申请号：US18771181

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Min Liang ,  Yen-Ping Wang ,  Jiun Yi Wu ,  Chen-Hua Yu ,  Kai-Chiang Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/5226

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

公开(公告)号：US20240355762A1

公开(公告)日：2024-10-24

申请号：US18760817

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121

Abstract: A device includes a redistribution structure, including conductive features; dielectric layers; and an internal support within a first dielectric layer of the dielectric layers, wherein the internal support is free of passive and active devices; a first interconnect structure attached to a first side of the redistribution structure; a second interconnect structure attached to the first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent the first interconnect structure, wherein the internal support laterally overlaps both the first interconnect structure and the second interconnect structure.

公开(公告)号：US20240355746A1

公开(公告)日：2024-10-24

申请号：US18761884

申请日：2024-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chieh-Yen Chen ,  Chuei-Tang Wang ,  Chung-Hao Tsai

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/5381 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/16146 ,  H01L2224/16165 ,  H01L2224/818 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/182

Abstract: A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.

公开(公告)号：US20240337800A1

公开(公告)日：2024-10-10

申请号：US18746934

申请日：2024-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia

IPC: G02B6/43 ,  G02B6/12 ,  G02B6/42 ,  H01S5/02326

CPC classification number: G02B6/43 ,  G02B6/4206 ,  G02B6/4214 ,  G02B6/4274 ,  H01S5/02326 ,  G02B6/12002 ,  G02B6/12004

Abstract: A semiconductor package includes a first interposer having a first substrate, a first redistribution structure over a first side of the first substrate, and a first waveguide over the first redistribution structure and proximate to a first side of the first interposer, where the first redistribution structure is between the first substrate and the first waveguide. The semiconductor package further includes a photonic package attached to the first side of the first interposer, where the photonic package includes: an electronic die, and a photonic die having a plurality of dielectric layers and a second waveguide in one of the plurality of dielectric layers, where a first side of the photonic die is attached to the electronic die, and an opposing second side of the photonic die is attached to the first side of the first interposer, where the second waveguide is proximate to the second side of the photonic die.