公开(公告)号：US08569795B2

公开(公告)日：2013-10-29

申请号：US13217472

申请日：2011-08-25

申请人： Hiroshi Kono ,  Yukio Nakabayashi ,  Takashi Shinohe ,  Makoto Mizukami

发明人： Hiroshi Kono ,  Yukio Nakabayashi ,  Takashi Shinohe ,  Makoto Mizukami

IPC分类号： H01L33/32 ,  H01L29/80 ,  H01L29/16 ,  H01L27/11 ,  H01L27/10

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/66068 ,  H01L29/7813

摘要： A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon carbide region and the third silicon carbide region; and a fourth electrode formed on the second principal surface of the silicon carbide substrate.

摘要翻译： 实施例的半导体器件包括：碳化硅衬底，其包括第一和第二主表面; 设置在碳化硅衬底的第一主表面上的第一导电型第一碳化硅层; 形成在所述第一碳化硅层的表面上的第二导电型第一碳化硅区; 形成在所述第一碳化硅区域的表面上的第一导电型第二碳化硅区域; 形成在所述第一碳化硅区域的表面上的第二导电型第三碳化硅区域; 连续形成在所述第一碳化硅层，所述第一碳化硅区域和所述第二碳化硅区域的表面上的栅极绝缘膜; 形成在所述栅极绝缘膜上的由碳化硅形成的第一电极; 形成在第一电极上的第二电极; 用于覆盖第一和第二电极的层间绝缘膜; 电连接到第二碳化硅区域和第三碳化硅区域的第三电极; 以及形成在碳化硅衬底的第二主表面上的第四电极。

公开(公告)号：US20130137253A1

公开(公告)日：2013-05-30

申请号：US13705610

申请日：2012-12-05

申请人： Hiroshi KONO ,  Takashi Shinohe

发明人： Hiroshi KONO ,  Takashi Shinohe

IPC分类号： H01L21/04

CPC分类号： H01L21/04 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802

摘要： A semiconductor device includes: a silicon carbide substrate having first and second main surfaces; a first silicon carbide layer provided on the first main surface of the silicon carbide substrate; first silicon carbide regions formed on a surface of the first silicon carbide layer; second and third silicon carbide regions formed on respective surfaces of the first silicon carbide regions; a fourth silicon carbide region formed between facing first silicon carbide regions with the first silicon carbide layer therebetween; a gate insulating film formed continuously on surfaces of the first silicon carbide regions, the first silicon carbide layer, and the fourth silicon carbide region; a gate electrode formed on the gate insulating film; an interlayer insulating film covering the gate electrode; a first electrode electrically connected to the second and third silicon carbide regions; and a second electrode formed on the second main surface of the silicon carbide substrate.

摘要翻译： 半导体器件包括：具有第一和第二主表面的碳化硅衬底; 设置在所述碳化硅衬底的所述第一主表面上的第一碳化硅层; 第一碳化硅区域形成在第一碳化硅层的表面上; 形成在第一碳化硅区域的相应表面上的第二和第三碳化硅区域; 形成在面对的第一碳化硅区域之间的第四碳化硅区域，其间具有第一碳化硅层; 在第一碳化硅区域，第一碳化硅层和第四碳化硅区域的表面上连续形成的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 覆盖栅电极的层间绝缘膜; 电连接到第二和第三碳化硅区域的第一电极; 以及形成在碳化硅衬底的第二主表面上的第二电极。

公开(公告)号：US07947988B2

公开(公告)日：2011-05-24

申请号：US12199848

申请日：2008-08-28

申请人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Johji Nishio

发明人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Johji Nishio

IPC分类号： H01L29/15

CPC分类号： H01L29/7802 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395

摘要： A semiconductor device includes an SiC substrate, a first SiC layer of first conductivity provided on the substrate, a second SiC layer of second conductivity provided on the first SiC layer, first and second SiC regions provided in the second SiC layer, facing each other and having the same depth, a third SiC region extending through the first SiC region and reaching the first SiC layer, a gate insulator formed on the first and second SiC regions and the second SiC layer interposed therebetween, a gate electrode formed on the gate insulator, a first contact of first conductivity formed on the second SiC region, a second contact of second conductivity formed on the second SiC region, reaching the second SiC layer through the second SiC region, and a top electrode formed on the first and second contacts, and a bottom electrode formed on a back surface of the substrate.

摘要翻译： 半导体器件包括SiC衬底，设置在衬底上的第一导电性第一SiC层，设置在第一SiC层上的第二导电性第二SiC层，设置在第二SiC层中的第一和第二SiC区域彼此面对， 具有相同深度的第三SiC区域延伸穿过第一SiC区域并到达第一SiC层，形成在第一和第二SiC区域上的第二SiC层和形成在栅极绝缘体上的第二SiC层的栅绝缘体， 形成在第二SiC区域上的第一导电体的第一接触，形成在第二SiC区域上的第二导电体的第二接触通过第二SiC区域到达第二SiC层，以及形成在第一和第二接触体上的顶部电极，以及 形成在基板的背面上的底部电极。

公开(公告)号：US20100308343A1

公开(公告)日：2010-12-09

申请号：US12846400

申请日：2010-07-29

申请人： Takuma Suzuki ,  Hiroshi Kono ,  Takashi Shinohe

发明人： Takuma Suzuki ,  Hiroshi Kono ,  Takashi Shinohe

IPC分类号： H01L29/78 ,  H01L29/24

CPC分类号： H01L29/7802 ,  H01L21/0465 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7816

摘要： According to the embodiment, a semiconductor device includes an SiC substrate of a first or second conductivity type. An SiC layer of the first conductivity type is formed on a front surface of the substrate, a first SiC region of the second conductivity type is formed on the SiC layer, a second SiC region of the first conductivity type is formed within a surface of the first SiC region, a gate dielectric is continuously formed on the SiC layer, the second SiC region, and the surface of the first SiC region interposed between the SiC layer and the second SiC region, a gate electrode is formed on the gate dielectric, a first electrode is embedded in a trench selectively formed in a part where the first SiC region adjoins the second SiC region, and a second electrode is formed on a back surface of the substrate.

摘要翻译： 根据实施例，半导体器件包括第一或第二导电类型的SiC衬底。 第一导电类型的SiC层形成在基板的前表面上，第二导电类型的第一SiC区域形成在SiC层上，第一导电类型的第二SiC区域形成在 第一SiC区域，在SiC层，第二SiC区域和介于SiC层和第二SiC区域之间的第一SiC区域的表面上连续地形成栅极电介质，在栅极电介质上形成栅电极， 第一电极嵌入在第一SiC区域与第二SiC区域相邻的部分中选择性地形成的沟槽中，并且在衬底的背面上形成第二电极。

公开(公告)号：US07368783B2

公开(公告)日：2008-05-06

申请号：US11230492

申请日：2005-09-21

申请人： Makoto Mizukami ,  Takashi Shinohe

发明人： Makoto Mizukami ,  Takashi Shinohe

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7828 ,  H01L29/8083

摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a first electrode surrounding the first semiconductor region and buried at a deeper position than the first semiconductor region, a second semiconductor region formed on the second major surface of the substrate, a buried field relaxation layer formed in the lightly-doped semiconductor layer between a bottom surface of the first electrode and the second semiconductor region, including a first field relaxation layer of the first conductivity type and second field relaxation layers of the second conductivity type formed at two ends of the first field relaxation layer, second and third electrodes formed on the first and second semiconductor regions, respectively.

摘要翻译： 半导体器件包括第一导电类型的半导体衬底，形成在衬底的第一主表面上的第一导电类型的轻掺杂半导体层，形成在岛状区域上的第一导电类型的第一半导体区域 在所述轻掺杂半导体层上，包围所述第一半导体区并且埋藏在比所述第一半导体区更深的位置的第一电极，形成在所述衬底的所述第二主表面上的第二半导体区， 在第一电极的底表面和第二半导体区域之间的轻掺杂半导体层，包括第一导电类型的第一场弛豫层和形成在第一场弛豫层两端的第二导电类型的第二场弛豫层 ，形成在第一和第二半导体区域上的第二和第三电极， 分别。

公开(公告)号：US20080001159A1

公开(公告)日：2008-01-03

申请号：US11821740

申请日：2007-06-25

申请人： Chiharu Ota ,  Johji Nishio ,  Tetsuo Hatakeyama ,  Takashi Shinohe

发明人： Chiharu Ota ,  Johji Nishio ,  Tetsuo Hatakeyama ,  Takashi Shinohe

IPC分类号： H01L29/04

CPC分类号： H01L29/66712 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/872

摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type having a top surface and a bottom surface, a semiconductor layer of a first conductivity type formed on the top surface of the semiconductor substrate, and having an active region and an edge termination region surrounding the active region, a first semiconductor region of a second conductivity type formed in the edge termination region adjacent to an edge of the active region, a second semiconductor region of a second conductivity type buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with a surface of the semiconductor layer, a first electrode formed on the active region of the semiconductor layer and a part of the first semiconductor region, and a second electrode formed on the bottom surface of the semiconductor substrate.

摘要翻译： 半导体器件包括具有顶表面和底表面的第一导电类型的半导体衬底，形成在半导体衬底的顶表面上的第一导电类型的半导体层，并且具有活动区域和围绕 有源区域，形成在与有源区域的边缘相邻的边缘终端区域中的第二导电类型的第一半导体区域，第二导电类型的第二半导体区域以片状或网状掩埋在边缘终端区域中 形状基本上与半导体层的表面平行，形成在半导体层的有源区和第一半导体区的一部分上的第一电极和形成在半导体衬底的底表面上的第二电极。

公开(公告)号：US5962893A

公开(公告)日：1999-10-05

申请号：US586277

申请日：1996-01-16

申请人： Ichiro Omura ,  Takashi Shinohe

发明人： Ichiro Omura ,  Takashi Shinohe

IPC分类号： H01L21/04 ,  H01L29/24 ,  H01L29/417 ,  H01L29/739 ,  H01L29/772 ,  H01L29/78 ,  H01L29/786 ,  H01L31/108 ,  H01L31/113 ,  H01L29/47

CPC分类号： H01L29/66068 ,  H01L21/046 ,  H01L29/41741 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7722 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/7839 ,  H01L29/78618 ,  H01L31/108 ,  H01L31/113 ,  H01L29/1608 ,  Y10S257/902

摘要： An n-semiconductor layer is arranged on a low-resistance n-substrate. A drain electrode is in ohmic contact with the n-substrate. A source electrode forms a Schottky junction with the n-semiconductor layer. A gate electrode is arranged adjacent to the source electrode on the n-semiconductor layer through a gate insulating film. When a voltage is applied to the gate electrode to lower the Schottky barrier height at the interface between the source electrode and the n-semiconductor layer, electrons are injected from the source electrode into the n-semiconductor layer, and a current flows in the semiconductor device. A diffusion layer which prevents a decrease in manufacturing time is not required to form in the n-semiconductor layer, and a channel which causes an increase in ON state voltage is not present.

摘要翻译： 在低电阻n衬底上设置n半导体层。 漏电极与n衬底欧姆接触。 源电极与n半导体层形成肖特基结。 栅极通过栅极绝缘膜与n型半导体层上的源电极相邻设置。 当向栅电极施加电压以降低源电极和n半导体层之间的界面处的肖特基势垒高度时，电子从源电极注入到n半导体层中，并且电流在半导体 设备。 不需要在n半导体层中形成防止制造时间的降低的扩散层，并且不存在导致ON状态电压增加的沟道。

公开(公告)号：US5793065A

公开(公告)日：1998-08-11

申请号：US483325

申请日：1995-06-07

申请人： Takashi Shinohe ,  Kazuya Nakayama ,  Minami Takeuchi ,  Masakazu Yamaguchi ,  Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa

发明人： Takashi Shinohe ,  Kazuya Nakayama ,  Minami Takeuchi ,  Masakazu Yamaguchi ,  Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa

IPC分类号： H01L29/423 ,  H01L29/745 ,  H01L29/749 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7455 ,  H01L29/42308 ,  H01L29/749

摘要： Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.

公开(公告)号：US08835288B2

公开(公告)日：2014-09-16

申请号：US13407249

申请日：2012-02-28

申请人： Johji Nishio ,  Masaru Furukawa ,  Hiroshi Kono ,  Takashi Shinohe

发明人： Johji Nishio ,  Masaru Furukawa ,  Hiroshi Kono ,  Takashi Shinohe

IPC分类号： H01L21/265 ,  H01L21/425 ,  H01L21/04 ,  H01L29/66 ,  H01L29/861 ,  H01L29/872 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16

CPC分类号： H01L21/046 ,  H01L21/045 ,  H01L21/049 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/8613 ,  H01L29/872

摘要： A method of manufacturing a silicon carbide semiconductor device of an embodiment includes: implanting ions in a silicon carbide substrate; performing first heating processing of the silicon carbide substrate in which the ions are implanted; and performing second heating processing of the silicon carbide substrate for which the first heating processing is performed, at a temperature lower than the first heating processing.

摘要翻译： 制造实施例的碳化硅半导体器件的方法包括：将离子注入碳化硅衬底中; 对其中注入离子的碳化硅衬底进行第一加热处理; 在低于第一加热处理的温度下进行进行了第一加热处理的碳化硅基板的第二加热处理。

公开(公告)号：US08796694B2

公开(公告)日：2014-08-05

申请号：US12407048

申请日：2009-03-19

申请人： Tetsuo Hatakeyama ,  Takashi Shinohe

发明人： Tetsuo Hatakeyama ,  Takashi Shinohe

IPC分类号： H01L29/15

CPC分类号： H01L29/7802 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608

摘要： A semiconductor device includes a semiconductor substrate made of silicon carbide and having a surface, a normal vector for the surface having an off angle with respect to a direction or a direction, a semiconductor layer of a first conductivity type formed on the semiconductor substrate, a first semiconductor region of a second conductivity type formed in a surface region of the semiconductor layer, a source region of a first conductivity type formed in a surface region of the first semiconductor region, a second semiconductor region of a second conductivity type formed in the surface region of the semiconductor layer, contacting the first semiconductor region, and having a bottom surface lower than a bottom surface of the first semiconductor region, wherein at least one end of the bottom surface of the second semiconductor region is perpendicular to an off angle direction.

摘要翻译： 半导体器件包括由碳化硅制成并具有表面的半导体衬底，表面的法向矢量相对于<0001>方向或<000-1>方向具有偏离角，第一导电性的半导体层 形成在所述半导体衬底上的第一半导体区域，形成在所述半导体层的表面区域中的第二导电类型的第一半导体区域，形成在所述第一半导体区域的表面区域中的第一导电类型的源极区域， 形成在所述半导体层的表面区域中的第二导电类型，与所述第一半导体区域接触，并且具有低于所述第一半导体区域的底表面的底表面，其中所述第二半导体区域的底表面的至少一个端部 垂直于偏角方向。