公开(公告)号：US10546626B2

公开(公告)日：2020-01-28

申请号：US15944666

申请日：2018-04-03

Applicant: Texas Instruments Incorporated

Inventor： Robert C. Baumann ,  John A. Rodriguez

IPC: G11C11/22

Abstract: A system includes a ferroelectric random access memory (FRAM) array having one or more memory elements. A cycle controller cycles data to be fixed in a subset of the one or more memory elements by reading or writing the data a predetermined number of times to fix the data to a non-volatile stable state.

公开(公告)号：US20180188987A1

公开(公告)日：2018-07-05

申请号：US15852618

申请日：2017-12-22

Applicant: Texas Instruments Incorporated

Inventor： John A. Rodriguez ,  Robert C. Baumann ,  Richard A. Bailey

IPC: G06F3/06 ,  G06F7/58 ,  G11C11/22

CPC classification number: G06F3/0623 ,  G06F3/0638 ,  G06F3/0679 ,  G06F7/588 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275

Abstract: Disclosed embodiments relate to generating random numbers using two transistor, two capacitor (2T-2C) ferroelectric memory cells. In accordance with one disclosed embodiment, an n-bit random number can be generated by writing to a uniform data pattern to a set of n 2T-2C ferroelectric memory cells in a 1T-1C mode so that all ferroelectric capacitors of the n 2T-2C cells have a polarization state corresponding to the same data value (e.g., all 0's or all 1's). The n 2T-2C cells are then read in a 2T-2C mode, so that a random bit (a 0 or 1) is produced for each cell, resulting in an n-bit random number. The n-bit random number is stored in the n 2T-2C ferroelectric memory cells by a rewrite operation. Such random numbers are useful for many purposes, including security, such as authentication, integrity checking, and encryption, and for identification.

公开(公告)号：US09070575B2

公开(公告)日：2015-06-30

申请号：US13953476

申请日：2013-07-29

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  John A. Rodriguez ,  Huang-Chun Wen ,  Steven Craig Bartling

IPC: H01L21/02 ,  H01L27/08 ,  H01L27/115 ,  H01L29/92 ,  H01L49/02 ,  H01L27/06 ,  H01L27/02

CPC classification number: H01L27/0805 ,  H01L27/0207 ,  H01L27/06 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55 ,  H01L29/92

Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.

Abstract translation: 用于集成去耦电容器的铁电电容器结构等。 铁电电容器结构包括在电压节点之间彼此串联连接的两个或更多个铁电电容器。 铁电电容器的串联连接减少了施加的电压，使得能够使用由MOCVD沉积的诸如PZT的粗铁电介质材料。 串联电容器的匹配结构以及每个电容器的施加电压的均匀极性有利于降低跨任何一个电容器的最大电压，从而降低了介质击穿的难度。

公开(公告)号：US20130313679A1

公开(公告)日：2013-11-28

申请号：US13953476

申请日：2013-07-29

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  John A. Rodriguez ,  Huang-Chun Wen ,  Steven Craig Bartling

IPC: H01L27/08 ,  H01L27/06

CPC classification number: H01L27/0805 ,  H01L27/0207 ,  H01L27/06 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55 ,  H01L29/92

Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.

Abstract translation: 用于集成去耦电容器的铁电电容器结构等。 铁电电容器结构包括在电压节点之间彼此串联连接的两个或更多个铁电电容器。 铁电电容器的串联连接减少了施加的电压，使得能够使用由MOCVD沉积的诸如PZT的粗铁电介质材料。 串联电容器的匹配结构以及每个电容器的施加电压的均匀极性有利于降低跨任何一个电容器的最大电压，从而降低了介质击穿的难度。

公开(公告)号：US10290362B2

公开(公告)日：2019-05-14

申请号：US15837451

申请日：2017-12-11

Applicant: Texas Instruments Incorporated

Inventor： Carl Z. Zhou ,  John A. Rodriguez ,  Richard A. Bailey

IPC: G11C11/22 ,  G11C29/50

Abstract: A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM array are tested at various reference voltage levels, after programming to a high polarization capacitance data state and a relaxation time at an elevated temperature. Fail bit counts of the sample groups at the various reference voltage levels are used to derive a test reference voltage, against which all of the FRAM cells in the integrated circuit are then tested after preconditioning (i.e., programming) and another relaxation interval at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure.

公开(公告)号：US20180374861A1

公开(公告)日：2018-12-27

申请号：US16056827

申请日：2018-08-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Huang-Chun Wen ,  Richard Allen Bailey ,  Antonio Guillemo Acosta ,  John A. Rodriguez ,  Scott Robert Summerfelt ,  Kemal Tamer San

IPC: H01L27/11507 ,  H01L21/02 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

公开(公告)号：US20180102184A1

公开(公告)日：2018-04-12

申请号：US15837451

申请日：2017-12-11

Applicant: Texas Instruments Incorporated

Inventor： Carl Z. Zhou ,  John A. Rodriguez ,  Richard A. Bailey

IPC: G11C29/50 ,  G11C11/22

CPC classification number: G11C29/50016 ,  G11C11/2275 ,  G11C29/50008

Abstract: A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM array are tested at various reference voltage levels, after programming to a high polarization capacitance data state and a relaxation time at an elevated temperature. Fail bit counts of the sample groups at the various reference voltage levels are used to derive a test reference voltage, against which all of the FRAM cells in the integrated circuit are then tested after preconditioning (i.e., programming) and another relaxation interval at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure.

公开(公告)号：US09552880B2

公开(公告)日：2017-01-24

申请号：US15019698

申请日：2016-02-09

Applicant: Texas Instruments Incorporated

Inventor： Carl Z. Zhou ,  John A. Rodriguez ,  Richard A. Bailey

IPC: G11C11/22 ,  G11C14/00

CPC classification number: G11C14/0072 ,  G11C11/221 ,  G11C11/2273 ,  G11C29/50016 ,  G11C29/70

Abstract: A reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays for stuck bits. The FRAM devices are subjected to a high temperature bake in wafer form. A “shmoo” of the reference voltage is performed, at an elevated temperature, for each device to identify a first reference voltage at which a first cell in the device fails a read of its low polarization capacitance data state, and a second reference voltage at which a selected number of cells in the device fail the read. The slope of the line between the first and second reference voltages, in the cumulative fail bit count versus reference voltage plane, is compared with a slope limit to determine whether any stuck bits are present in the device.

Abstract translation: 集成电路的可靠性屏幕，包括用于卡住位的铁电随机存取存储器（FRAM）阵列。 对FRAM器件进行晶片形式的高温烘烤。 在升高的温度下，对于每个器件执行参考电压的“shmoo”，以识别第一参考电压，在该第一参考电压下，器件中的第一单元不能读取其低极化电容数据状态，第二参考电压 设备中选定数量的单元格读取失败。 将累积故障位计数与参考电压平面中的第一和第二参考电压之间的线的斜率与斜率限制进行比较，以确定器件中是否存在任何卡位。

公开(公告)号：US20160086960A1

公开(公告)日：2016-03-24

申请号：US14728683

申请日：2015-06-02

Applicant: Texas Instruments Incorporated

Inventor： Huang-Chun Wen ,  Richard Allen Bailey ,  Antonio Guillermo Acosta ,  John A. Rodriguez ,  Scott Robert Summerfelt ,  Kemal Tamer San

IPC: H01L27/115 ,  H01L21/02 ,  H01L29/78 ,  H01L23/31 ,  H01L23/29 ,  H01L21/326 ,  H01L23/00

CPC classification number: H01L27/11507 ,  H01L21/02118 ,  H01L21/0217 ,  H01L21/02197 ,  H01L21/02318 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/07025 ,  H01L2924/014

Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

Abstract translation: 固化施加到铁电集成电路的表面的钝化层，以增强铁电结构的极化特性。 在制造有源器件之后，将钝化层（例如聚酰亚胺）施加到铁电集成电路的表面。 钝化层通过暴露于低于铁电材料的居里温度的高温固化，持续时间短，例如十分钟左右。 可以使用变频微波能量来实现这种固化。 固化的钝化层达到拉伸应力状态，结果赋予了下伏的铁电材料的压应力。 在固化过程之前极化铁电材料可以进一步提高极化。

公开(公告)号：US20150357050A1

公开(公告)日：2015-12-10

申请号：US14519894

申请日：2014-10-21

Applicant: Texas Instruments Incorporated

Inventor： Richard Bailey ,  John A. Rodriguez

IPC: G11C29/50 ,  G11C11/22

CPC classification number: G11C29/50016 ,  G11C11/225

Abstract: A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. A reference voltage level is determined for each integrated circuit being tested, corresponding to the read of a high polarization capacitance data state. A number of FRAM cells in the integrated circuit are programmed to that data state, and then read at an elevated temperature, with the number of failing cells compared against a pass/fail threshold to determine whether the integrated circuit is vulnerable to long-term data retention failure.

Abstract translation: 包括铁电随机存取存储器（FRAM）阵列的集成电路的数据保持可靠性屏幕。 对于正在测试的每个集成电路，对应于高偏振电容数据状态的读取，确定参考电压电平。 集成电路中的多个FRAM单元被编程为该数据状态，然后在升高的温度读取，故障单元的数量与通过/失败阈值进行比较，以确定集成电路是否易受长期数据的影响 保留失败。