公开(公告)号：US07842977B2

公开(公告)日：2010-11-30

申请号：US11675460

申请日：2007-02-15

申请人： Stefan Jakschik ,  Thomas Hecht

发明人： Stefan Jakschik ,  Thomas Hecht

IPC分类号： H01L29/78

CPC分类号： H01L21/28026 ,  H01L21/28061 ,  H01L21/823842 ,  H01L29/42372 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/7833 ,  H01L29/7845

摘要： A gate electrode structure comprises at least one bi-layer, wherein each bi-layer comprises a plating film and a stress amplifier film. The plating film includes a poly-crystalline material. The stress amplifier film determines the crystallization result of the poly-crystalline material, wherein a mechanical stress induced through the plating layer is amplified. Tensile or compressive strain may be induced in a crystalline substrate. Electron or hole mobility may be increased and on-resistance characteristics of a MOS field effect transistor may be improved.

摘要翻译： 栅电极结构包括至少一个双层，其中每个双层包括镀膜和应力放大膜。 镀膜包括多晶材料。 应力放大器膜确定多晶材料的结晶结果，其中通过镀层诱导的机械应力被放大。 可能在结晶底物中诱导拉伸或压缩应变。 可以增加电子或空穴迁移率，并可提高MOS场效应晶体管的导通电阻特性。

公开(公告)号：US20060202250A1

公开(公告)日：2006-09-14

申请号：US11076021

申请日：2005-03-10

申请人： Thomas Hecht ,  Uwe Schroeder ,  Till Schloesser ,  Stefan Jakschik ,  Alejandro Avellan

发明人： Thomas Hecht ,  Uwe Schroeder ,  Till Schloesser ,  Stefan Jakschik ,  Alejandro Avellan

IPC分类号： H01L29/94

CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L28/82

摘要： A storage capacitor, suitable for use in a DRAM cell, is at least partially formed above a substrate surface and includes: a storage electrode at least partially formed above the substrate surface, a dielectric layer formed adjacent the storage electrode, and a counter electrode formed adjacent the dielectric layer, the counter electrode being isolated from the storage electrode by the dielectric layer, wherein the storage electrode is formed as a body which is delimited by at least one curved surface having a center of curvature outside the body in a plane parallel to the substrate surface. According to another configuration, the storage electrode is formed as a body which is delimited by at least one set having two contiguous planes, the two planes extending perpendicularly with respect to the substrate surface, a point of intersection of normals of the two planes lying outside the body.

摘要翻译： 适用于DRAM单元的存储电容器至少部分地形成在衬底表面之上，并且包括：至少部分地形成在衬底表面上方的存储电极，与存储电极相邻形成的电介质层和形成的对电极 所述对置电极通过所述电介质层与所述存储电极隔离，其中所述存储电极形成为主体，所述主体由平行于所述电介质层的平面中的具有在所述主体外部的曲率中心的至少一个曲面限定 基材表面。 根据另一种结构，存储电极形成为由具有两个相邻平面的至少一组限定的主体，两个平面相对于基板表面垂直延伸，两个平面的法线相交点位于外部 身体。

公开(公告)号：US07531406B2

公开(公告)日：2009-05-12

申请号：US11399811

申请日：2006-04-07

申请人： Alejandro Avellan ,  Thomas Hecht ,  Stefan Jakschik ,  Uwe Schroeder

发明人： Alejandro Avellan ,  Thomas Hecht ,  Stefan Jakschik ,  Uwe Schroeder

IPC分类号： H01L21/8234

CPC分类号： H01L28/65 ,  H01L27/1087 ,  H01L29/66181

摘要： An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric (130) or the connection electrode (120, 140) are formed in such a manner that transient polarization effects are prevented or at least reduced.

摘要翻译： 制造诸如DRAM半导体存储器或场效应晶体管的电气部件。 制造具有电介质（130）和至少一个连接电极（120,140）的至少一个电容器。 为了使得制造的电容器即使对于非常小的电容器结构也具有最佳的存储特性，电介质（130）或连接电极（120,140）形成为使得瞬态极化效应被防止或至少减小。

公开(公告)号：US20060134871A1

公开(公告)日：2006-06-22

申请号：US11017194

申请日：2004-12-20

申请人： Stefan Jakschik ,  Matthias Goldbach ,  Thomas Mikolajick ,  Thomas Hecht

发明人： Stefan Jakschik ,  Matthias Goldbach ,  Thomas Mikolajick ,  Thomas Hecht

IPC分类号： H01L21/336

CPC分类号： H01L29/512 ,  H01L21/28282 ,  H01L29/42348 ,  H01L29/78 ,  H01L29/7923

摘要： Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.

公开(公告)号：US20080242097A1

公开(公告)日：2008-10-02

申请号：US11729360

申请日：2007-03-28

申请人： Tim Boescke ,  Annette Saenger ,  Stefan Jakschik ,  Christian Fachmann ,  Matthias Patz ,  Alejandro Avellan ,  Thomas Hecht ,  Jonas Sundqvist

发明人： Tim Boescke ,  Annette Saenger ,  Stefan Jakschik ,  Christian Fachmann ,  Matthias Patz ,  Alejandro Avellan ,  Thomas Hecht ,  Jonas Sundqvist

IPC分类号： H01L21/31 ,  H01L29/06

CPC分类号： H01L29/945 ,  C30B25/04 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/31616 ,  H01L21/31645

摘要： The invention refers to a selective deposition method. A substrate comprising at least one structured surface is provided. The structured surface comprises a first area and a second area. The first area is selectively passivated regarding reactants of a first deposition technique and the second area is activated regarding the reactants the first deposition technique. A passivation layer on the second area is deposited via the first deposition technique. The passivation layer is inert regarding a precursors selected from a group of oxidizing reactants. A layer is deposited in the second area using a second atomic layer deposition technique as second deposition technique using the precursors selected form the group of oxidizing reactants.

摘要翻译： 本发明涉及选择性沉积方法。 提供了包括至少一个结构化表面的衬底。 结构化表面包括第一区域和第二区域。 对于第一沉积技术的反应物，第一区域被选择性地钝化，并且第二区域被激活关于第一沉积技术的反应物。 通过第一沉积技术沉积第二区域上的钝化层。 对于选自一组氧化反应物的前体，钝化层是惰性的。 使用第二原子层沉积技术将层沉积在第二区域中，作为使用从氧化反应物组中选择的前体的第二沉积技术。

公开(公告)号：US07358187B2

公开(公告)日：2008-04-15

申请号：US11147892

申请日：2005-06-08

申请人： Thomas Hecht ,  Stefan Jakschik ,  Uwe Schröder

发明人： Thomas Hecht ,  Stefan Jakschik ,  Uwe Schröder

IPC分类号： H01L21/31 ,  H01L21/44

CPC分类号： C23C16/0281 ,  C23C14/046 ,  C23C16/045 ,  H01L21/0228 ,  H01L21/28562 ,  H01L21/3141 ,  H01L21/76877 ,  H01L22/26

摘要： The present invention provides a coating process for patterned substrate surfaces, in which a substrate (101) is provided, the substrate having a surface (105) which is patterned in a substrate patterning region (102) and has one or more trenches (106) that are to be filled to a predetermined filling height (205), a catalyst layer (201) is introduced into the trenches (106) that are to be filled, a reaction layer (202) is deposited catalytically in the trenches (106) that are to be filled, the catalytically deposited reaction layer (202) is densified in the trenches (106) that are to be filled, and the introduction of the catalyst layer (201) and the catalytic deposition of the reaction layer (202) are repeated until the trenches (106) that are to be filled have been filled to the predetermined filling height (205).

摘要翻译： 本发明提供一种用于图案化衬底表面的涂覆方法，其中提供衬底（101），该衬底具有在衬底图案化区域（102）中被图案化并具有一个或多个沟槽（106）的表面（105） 将其填充到预定的填充高度（205），将催化剂层（201）引入要填充的沟槽（106）中，在沟槽（106）中催化沉积反应层（202），其中 要填充的催化沉积反应层（202）在要填充的沟槽（106）中致密化，并且重复引入催化剂层（201）和催化沉积反应层（202） 直到要填充的沟槽（106）已经被填充到预定填充高度（205）。

公开(公告)号：US07157371B2

公开(公告)日：2007-01-02

申请号：US10653599

申请日：2003-09-02

申请人： Thomas Hecht ,  Uwe Schroeder ,  Harald Seidl ,  Martin Gutsche ,  Stefan Jakschik ,  Stephan Kudelka ,  Albert Birner

发明人： Thomas Hecht ,  Uwe Schroeder ,  Harald Seidl ,  Martin Gutsche ,  Stefan Jakschik ,  Stephan Kudelka ,  Albert Birner

IPC分类号： H01L21/44

CPC分类号： H01L27/11502 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/28061 ,  H01L21/31138 ,  H01L21/31604 ,  H01L21/3162 ,  H01L21/76802 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L27/11507 ,  H01L28/57 ,  H01L29/0895 ,  H01L29/4941

摘要： A dielectric barrier layer composed of a metal oxide is applied in thin layers with a thickness of less than 20 nanometers in the course of processing semiconductor devices by sequential gas phase deposition or molecular beam epitaxy in molecular individual layers on differently structured base substrates. The method allows, inter alias, effective conductive diffusion barriers to be formed from a dielectric material, an optimization of the layer thickness of the barrier layer, an increase in the temperature budget for subsequent process steps, and a reduction in the effort for removing the temporary barrier layers.

摘要翻译： 由金属氧化物构成的电介质阻挡层通过在不同结构的基底衬底上的分子单层中的顺序气相沉积或分子束外延处理半导体器件的过程中以小于20纳米的厚度施加。 该方法允许间隔地从电介质材料形成有效的导电扩散阻挡层，优化阻挡层的层厚度，随后的工艺步骤的温度预算的增加以及用于去除 临时阻隔层。

公开(公告)号：US07132337B2

公开(公告)日：2006-11-07

申请号：US11017194

申请日：2004-12-20

申请人： Stefan Jakschik ,  Matthias Goldbach ,  Thomas Mikolajick ,  Thomas Hecht

发明人： Stefan Jakschik ,  Matthias Goldbach ,  Thomas Mikolajick ,  Thomas Hecht

IPC分类号： H01L21/336

CPC分类号： H01L29/512 ,  H01L21/28282 ,  H01L29/42348 ,  H01L29/78 ,  H01L29/7923

摘要： Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.

摘要翻译： 电荷捕获区域布置在栅电极的下边缘下方彼此分离。 源极/漏极区域以相对于电荷俘获区域的自对准方式通过在低能量下的掺杂工艺形成，以形成仅在电荷俘获区域下方仅小的距离的浅结。 自对准确保了大量的编程擦除周期，具有高效率和良好的数据保留，因为注入相反符号的电荷载体的位置被狭义地和精确地定义。

公开(公告)号：US06953722B2

公开(公告)日：2005-10-11

申请号：US10425461

申请日：2003-04-29

申请人： Harald Seidl ,  Martin Gutsche ,  Thomas Hecht ,  Stefan Jakschik ,  Stephan Kudelka ,  Uwe Schröder ,  Matthias Schmeide

发明人： Harald Seidl ,  Martin Gutsche ,  Thomas Hecht ,  Stefan Jakschik ,  Stephan Kudelka ,  Uwe Schröder ,  Matthias Schmeide

IPC分类号： H01L21/311 ,  H01L21/8242

CPC分类号： H01L27/10867 ,  H01L21/31133

摘要： In a method for forming patterned ceramic layers, a ceramic material is deposited on a substrate and is subsequently densified by heat treatment, for example. In this case, the initially amorphous material is converted into a crystalline or polycrystalline form. In order that the now crystalline material can be removed again from the substrate, imperfections are produced in the ceramic material, for example by ion implantation. As a result, the etching medium can more easily attack the ceramic material, so that the latter can be removed with a higher etching rate. Through inclined implantation, the method can be performed in a self-aligning manner and the ceramic material can be removed on one side, by way of example, in trenches or deep trench capacitors.

摘要翻译： 在用于形成图案化陶瓷层的方法中，陶瓷材料沉积在基底上，并随后通过热处理致密化。 在这种情况下，最初的无定形材料被转化为结晶或多晶形式。 为了现在的结晶材料可以再次从衬底去除，例如通过离子注入在陶瓷材料中产生缺陷。 结果，蚀刻介质可以更容易地侵蚀陶瓷材料，使得后者可以以更高的蚀刻速率被去除。 通过倾斜注入，该方法可以以自对准的方式进行，并且陶瓷材料可以通过例如在沟槽或深沟槽电容器中被一侧除去。

公开(公告)号：US20070059893A1

公开(公告)日：2007-03-15

申请号：US11518504

申请日：2006-09-07

申请人： Stephan Kudelka ,  Peter Moll ,  Stefan Jakschik ,  Odo Wunnicke

发明人： Stephan Kudelka ,  Peter Moll ,  Stefan Jakschik ,  Odo Wunnicke

IPC分类号： H01L21/336

CPC分类号： H01L28/90 ,  H01L27/10814 ,  H01L27/10852

摘要： A method produces stacked capacitors for dynamic memory cells, in which a number of trenches (48) are formed in the masking layer (40), each trench (48) being arranged above a respective contact plug (26) and extending from the top (42) of the masking layer (40) to the contact plugs (26). A conductive layer (50) covers the side walls (49) of the trenches (48) and the contact plugs (26) in order to form a first electrode (60) of a stacked capacitor (12). In an upper region (63), which is remote from the contact stack (26), the conductive layer (50) is replaced by an insulating layer, so that it is not possible for a short circuit to arise in the event of any adhesion between adjacent electrodes.

摘要翻译： 一种方法产生用于动态存储单元的堆叠电容器，其中在掩模层（40）中形成有多个沟槽（48），每个沟槽（48）布置在相应的接触插塞（26）的上方并从顶部 屏蔽层（40）的至少部分（42）连接到接触插塞（26）。 为了形成叠层电容器（12）的第一电极（60），导电层（50）覆盖沟槽（48）的侧壁（49）和接触插塞（26）。 在远离接触堆叠（26）的上部区域（63）中，导电层（50）由绝缘层代替，使得在任何粘附的情况下不可能出现短路 在相邻电极之间。