公开(公告)号：US20230274940A1

公开(公告)日：2023-08-31

申请号：US18312650

申请日：2023-05-05

Applicant: Tokyo Electron Limited

Inventor： Michael MURPHY ,  Jodi GRZESKOWIAK ,  Anton J. DEVILLIERS

IPC: H01L21/308 ,  H01L21/027 ,  H01L21/033 ,  G03F7/00 ,  G03F7/11

CPC classification number: H01L21/3086 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/0338 ,  G03F7/0035 ,  G03F7/11

Abstract: In method of patterning a substrate, a first relief pattern is formed based on a first layer deposited over a substrate. Openings in the first relief pattern are filled with a reversal material. The first relief pattern is then removed from the substrate and the reversal material remains on the substrate to define a second relief pattern. A fill material is deposited over the substrate that is in contact with the second relief pattern, and sensitive to a photo-acid generated from a photo-acid generator in the second relief pattern. Selected portions of the second relief pattern are exposed to a first actinic radiation to generate the photo-acid in the selected portions of the second relief pattern. The photo-acid are driven from the selected portions of the second relief pattern into portions of the fill material so that the portions of the fill material to become soluble to a predetermined developer.

公开(公告)号：US20220350247A1

公开(公告)日：2022-11-03

申请号：US17735732

申请日：2022-05-03

Applicant: Tokyo Electron Limited

Inventor： Anton J. DEVILLIERS

IPC: G03F7/09 ,  H01L21/311 ,  H01L21/027

Abstract: A method of patterning a substrate includes forming a multilayer photoresist stack on a substrate. The multilayer photoresist stack includes a dry photoresist layer, deposited by vapor deposition, over a wet photoresist layer deposited by spin-on deposition. A first relief pattern is formed in the wet photoresist layer by exposure to a first pattern of actinic radiation of a first wavelength and development of developable portions of the wet photoresist layer using a first development process. The first relief pattern uncovers portions of the dry photoresist layer. A second relief pattern is formed in the dry photoresist layer by exposure to a second pattern of actinic radiation of a second wavelength and development of developable portions of the dry photoresist layer using a second development process. The developable portions of the dry photoresist layer are defined by the second pattern of actinic radiation and the first relief pattern.

公开(公告)号：US20220238328A1

公开(公告)日：2022-07-28

申请号：US17473248

申请日：2021-09-13

Applicant: Tokyo Electron Limited

Inventor： Anton J. DEVILLIERS ,  Daniel J. FULFORD ,  Anthony R. SCHEPIS ,  Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L21/027 ,  H01L23/16

Abstract: Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. For example, the method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof. The method can further include attaching the first side of the first semiconductor structure to a carrier substrate. The method can further include forming a stress film on a second side of the first semiconductor structure. The method can further include separating the carrier substrate from the first semiconductor structure. The method can further include cutting the stress film and the first semiconductor structure to define at least one chiplet. The method can further include bonding the at least one chiplet to a second semiconductor structure having a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

公开(公告)号：US20210351053A1

公开(公告)日：2021-11-11

申请号：US17381297

申请日：2021-07-21

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Anthony SCHEPIS ,  Anton J. DEVILLIERS

IPC: H01L21/67 ,  H01L23/544 ,  H01L21/027 ,  H01L23/528

Abstract: A method for marking a semiconductor substrate at the die level for providing unique authentication and serialization includes projecting a first pattern of actinic radiation onto a layer of photoresist on the substrate using mask-based photolithography, the first pattern defining semiconductor device structures and projecting a second pattern of actinic radiation onto the layer of photoresist using direct-write projection, the second pattern defining a unique wiring structure having a unique electrical signature.

公开(公告)号：US20200075574A1

公开(公告)日：2020-03-05

申请号：US16559923

申请日：2019-09-04

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Anton J. DEVILLIERS ,  Kandabara TAPILY

IPC: H01L27/02 ,  H01L27/092

Abstract: A semiconductor device includes: a substrate having a surface, the surface being planar; a first logic gate provided on the substrate and comprising a first field effect transistor (FET) having a first channel, and a first pair of source-drain regions; a second logic gate stacked over the first logic gate along a vertical direction perpendicular to the surface of the substrate, the second logic gate comprising a second FET having a second channel, and a second pair of source-drain regions; and a contact electrically connecting a source-drain region of the first FET to a source-drain region of the second FET such that at least a portion of current flowing between the first and second logic gate will flow along said vertical direction.

公开(公告)号：US20230326855A1

公开(公告)日：2023-10-12

申请号：US18331651

申请日：2023-06-08

Applicant: Tokyo Electron Limited

Inventor： Lars LIEBMANN ,  Jeffrey SMITH ,  Daniel CHANEMOUGAME ,  Anton J. DEVILLIERS

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/5283 ,  H01L21/76895 ,  H01L21/76877 ,  H01L23/5226

Abstract: Aspects of the present disclosure provide a method for fabricating a semiconductor device. For example, the method can include forming a first power rail, forming a first power input structure for coupling with a first terminal of a power source that is external of the semiconductor device to receive electrical power from the power source, forming an active device between the first power rail and the first power input structure, and forming a first middle-of-line rail with a plurality of layers. The first middle-of-line rail can be configured to deliver the electrical power from the first power input structure to the first power rail. The first power rail can provide the electrical power to the active device for operation. Topmost and bottommost ones of the layers of the first middle-of-line rail can be as high as and leveled with top and bottom surfaces of the active device, respectively.

公开(公告)号：US20230326738A1

公开(公告)日：2023-10-12

申请号：US17967257

申请日：2022-10-17

Applicant: Tokyo Electron Limited

Inventor： Anthony R. SCHEPIS ,  Daniel J. FULFORD ,  David C. CONKLIN ,  Anton J. DEVILLIERS

IPC: H01L21/02

CPC classification number: H01L21/02118 ,  H01L21/02318

Abstract: Methods described herein address the chuck degradation challenge that can result in wafer distortion upon wafer coupling, leading to downstream fabrication issues. Techniques include actively monitoring wear of a chuck and counteracting chuck degradation by wafer shape manipulation to maintain an ideal working surface. Techniques include using chuck-based flatness metrology and/or modeling based on previous wafer level results and/or historical database of chuck wear information.

公开(公告)号：US20220238380A1

公开(公告)日：2022-07-28

申请号：US17486189

申请日：2021-09-27

Applicant: Tokyo Electron Limited

Inventor： Anton J. DEVILLIERS ,  Daniel J. FULFORD ,  Anthony R. SCHEPIS ,  Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L21/822

Abstract: Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. The method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof, and attaching the first side to a carrier substrate. The method can further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure, and separating the carrier substrate from the first semiconductor structure. The method can further include cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet, and bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

公开(公告)号：US20210366792A1

公开(公告)日：2021-11-25

申请号：US17198936

申请日：2021-03-11

Applicant: Tokyo Electron Limited

Inventor： Daniel FULFORD ,  Anton J. DEVILLIERS

IPC: H01L21/66 ,  H01L21/67 ,  H01L23/00

Abstract: A method of microfabrication is provided. A substrate having a working surface and having a backside surface opposite to the working surface is received. The substrate has an initial wafer bow resulting from one or more micro fabrication processing steps executed on the working surface of the substrate. The initial wafer bow of the substrate is measured and the initial wafer bow is used to generate an initial wafer bow value that identifies a degree of first order wafer bowing of the substrate. A correction film recipe based on the initial wafer bow value is identified. The correction film recipe specifies parameters of a correction film to be deposited on the backside surface of the substrate to change wafer bow of the substrate from the initial wafer bow to a modified wafer bow. The correction film on the backside surface of the substrate according to the correction film recipe is deposited. The correction film physically modifies internal stresses on the substrate and causes the substrate to have a modified bow with the predetermined wafer bow value.

公开(公告)号：US20210088904A1

公开(公告)日：2021-03-25

申请号：US17023470

申请日：2020-09-17

Applicant: Tokyo Electron Limited

Inventor： Anton J. DEVILLIERS ,  Jodi GRZESKOWIAK ,  Daniel FULFORD ,  Richard A. FARRELL ,  Jeffrey SMITH

IPC: G03F7/039 ,  H01L21/027 ,  G03F7/16 ,  G03F7/30 ,  G03F7/20

Abstract: A method of forming a pattern on a substrate is provided. The method includes forming a first layer on an underlying layer of the substrate, where the first layer is patterned to have a first structure. The method also includes depositing a grafting material on side surfaces of the first structure, where the grafting material includes a solubility-shifting material. The method further includes diffusing the solubility-shifting material by a predetermined distance into a neighboring structure that abuts the solubility-shifting material, where the solubility-shifting material changes solubility of the neighboring structure in a developer, and removing soluble portions of the neighboring structure using the developer to form a second structure.