公开(公告)号：US20080280293A1

公开(公告)日：2008-11-13

申请号：US11795016

申请日：2006-01-11

Applicant: Toshihiro Tanaka ,  Koichi Ozaki ,  Aritoshi Iida ,  Masatsugu Hori ,  Yusuke Nakamura

Inventor： Toshihiro Tanaka ,  Koichi Ozaki ,  Aritoshi Iida ,  Masatsugu Hori ,  Yusuke Nakamura

IPC: C12Q1/68 ,  C07H21/04 ,  G01N33/566

CPC classification number: C12Q1/6883 ,  C12Q2600/156 ,  G01N33/566 ,  G01N33/6893 ,  G01N2333/705 ,  G01N2800/32 ,  G01N2800/324

Abstract: A gene polymorphism on a Toll-like receptor gene is analyzed and an inflammatory disease is examined based on the results of the analysis. A remedy for an inflammatory disease is screened by selecting a substance capable of altering the interaction between Toll-like receptor and galectin-2.

Abstract translation: 分析Toll样受体基因的基因多态性，并根据分析结果检测炎性疾病。 通过选择能够改变Toll样受体和半乳凝素-2的相互作用的物质来筛选炎性疾病的治疗方法。

公开(公告)号：US07339827B2

公开(公告)日：2008-03-04

申请号：US11147243

申请日：2005-06-08

Applicant: Kan Yasui ,  Digh Hisamoto ,  Toshihiro Tanaka ,  Takashi Yamaki

Inventor： Kan Yasui ,  Digh Hisamoto ,  Toshihiro Tanaka ,  Takashi Yamaki

IPC: G11C16/06 ,  G11C16/32 ,  G11C5/06 ,  G11C16/08 ,  G11C16/24

CPC classification number: G11C16/3418 ,  G11C16/0466 ,  G11C16/3427 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/792

Abstract: In connection with rise and fall of a word line bias, the present invention adopts a procedure such that a diffusion region voltage Vs on a memory transistor side is changed, and after the voltage Vs passes a certain intermediate value Vsx, a gate voltage Vmg of the memory transistor is changed. Alternatively, there is adopted a procedure such that the gate voltage Vmg of the memory transistor is changed, and after the voltage Vmg passes a certain intermediate value Vmgx, the diffusion layer voltage Vs on the memory transistor side is changed. The values of Vsx and Vmgx are determined from the magnitude of the electric field in a gate insulating film not causing FN tunneling electron injection that causes a change in threshold voltage and the magnitude of a potential barrier against holes not causing BTBT hot hole injection.

Abstract translation: 关于字线偏差的上升和下降，本发明采用使存储晶体管侧的扩散区电压Vs变化的过程，在电压Vs经过一定的中间值Vsx之后，栅极电压Vmg为 存储晶体管被改变。 或者，采用使存储晶体管的栅极电压Vmg改变的过程，并且在电压Vmg经过一定的中间值Vmgx之后，存储晶体管侧的扩散层电压Vs被改变。 Vsx和Vmgx的值由栅极绝缘膜中不引起FN隧穿电子注入的电场的大小确定，导致阈值电压的变化以及针对未引起BTBT热空穴注入的孔的势垒的大小。

公开(公告)号：US20070288817A1

公开(公告)日：2007-12-13

申请号：US11785537

申请日：2007-04-18

Applicant: Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masahiko Kimura ,  Isao Nakamura

Inventor： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masahiko Kimura ,  Isao Nakamura

IPC: G01R31/28

CPC classification number: G11C29/021 ,  G01R31/30 ,  G01R31/31703 ,  G01R31/31725 ,  G01R31/3187 ,  G06F11/24 ,  G11C16/04 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/5004

Abstract: A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.

Abstract translation: 其中可以容易地与其他LSI并行设置用于确定其本身产生的脉冲的电压或宽度的控制信息的半导体集成电路（LSI），并且可以容易地校正设置信息。 从外部评估装置，将预期值的电压重叠地提供给具有CPU和闪速存储器的多个LSI。 每个LSI包含比较电路，其比较期望的电压值和本身产生的升压电压。 CPU参考比较结果并优化用于改变升压电压的数据寄存器中的控制数据。 CPU控制比较电路和数据寄存器，并且以自完成方式进行修整，从而以并行方式容易地对多个LSI进行修整，并且总的测试时间减少。

公开(公告)号：US07286410B2

公开(公告)日：2007-10-23

申请号：US11195684

申请日：2005-08-03

Applicant: Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Takashi Yamaki

Inventor： Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Takashi Yamaki

IPC: G11C16/06

CPC classification number: G11C16/344

Abstract: A semiconductor integrated circuit has a first nonvolatile memory area and a second nonvolatile memory area to store information in accordance with a variable threshold voltage. At least one condition of the following conditions of the first nonvolatile memory area is made different from that of the second nonvolatile memory area: erase verify determination memory gate voltage, erase verify determination memory current, write verify determination memory gate voltage, write verify determination memory current, erase voltage, erase voltage application time, write voltage, and write voltage application time in the first nonvolatile memory area.

Abstract translation: 半导体集成电路具有第一非易失性存储区域和第二非易失性存储区域，用于根据可变阈值电压存储信息。 使第一非易失性存储区域的以下条件的至少一个条件与第二非易失性存储器区域的不同：擦除验证确定存储器栅极电压，擦除验证确定存储器电流，写入验证确定存储器栅极电压，写入验证确定存储器 第一非易失性存储器区域中的电流，擦除电压，擦除电压施加时间，写入电压和写入电压施加时间。

公开(公告)号：US07190615B2

公开(公告)日：2007-03-13

申请号：US10810672

申请日：2004-03-29

Applicant: Masamichi Fujito ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Ayako Kakuda ,  Akira Kato ,  Toshihiro Tanaka

Inventor： Masamichi Fujito ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Ayako Kakuda ,  Akira Kato ,  Toshihiro Tanaka

IPC: G11C11/34 ,  G11C5/06

CPC classification number: G11C7/18 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/26 ,  G11C16/28 ,  G11C16/30 ,  G11C2207/005 ,  G11C2216/22

Abstract: The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality of memory arrays, a first selector circuit selecting the first bit line for each of the memory arrays to connect the selected first bit line to the second bit line, and a sense amp arranged between the output of the first selector circuit and the second bit line. The hierarchal bit line structure having the divided memory arrays can reduce the input load capacity of the sense amp.

Abstract translation: 能够进行电气重写的片上非易失性存储器的读取速度增加。 非易失性存储器具有分层位线结构，其具有对多个存储器阵列中的每一个特定的第一位线，在多个存储器阵列之间共享的第二位线，第一选择器电路，用于为每个存储器阵列选择第一位线 将所选择的第一位线连接到第二位线，以及布置在第一选择器电路的输出和第二位线之间的感测放大器。 具有划分的存储器阵列的层次位线结构可以减小感测放大器的输入负载能力。

公开(公告)号：US07166220B2

公开(公告)日：2007-01-23

申请号：US10484776

申请日：2002-11-21

Applicant: Toshihiro Tanaka ,  Yosei Katsu ,  Satoshi Konishi

Inventor： Toshihiro Tanaka ,  Yosei Katsu ,  Satoshi Konishi

IPC: C02F3/30

CPC classification number: C02F3/121 ,  C02F3/1268 ,  C02F3/301 ,  Y02W10/15 ,  Y10S210/903

Abstract: A system and method for organic wastewater treatment through denitrification and nitrification processes. The system for treating organic wastewater includes a multistage treatment tank having at least two stages in series. Each stage has a denitrification tank and a nitrification tank connected in this order. The system includes a pipe for distributing feed water to the denitrification tank in each stage, a device for filtering and separating at least a part of an activated sludge mixed liquor present in at least one nitrification tank, and a pipe for supplying at least a part of the concentrated sludge mixed liquor obtained by the filtration and separation treatment to the denitrification tank.

Abstract translation: 一种通过反硝化和硝化过程进行有机废水处理的系统和方法。 用于处理有机废水的系统包括具有至少两个级联的多级处理槽。 每个阶段都有一个反硝化池和硝化池依次连接。 该系统包括用于在每个阶段向脱氮罐分配给水的管道，用于过滤和分离存在于至少一个硝化罐中的至少一部分活性污泥混合液的装置和用于供应至少一部分的管 通过过滤和分离处理获得的浓缩污泥混合液到脱氮槽中。

公开(公告)号：US20060243660A1

公开(公告)日：2006-11-02

申请号：US10551818

申请日：2004-03-29

Applicant: Kazumasa Kamachi ,  Yasuhiro Honma ,  Toshihiro Tanaka ,  Toshio Tsukamoto

Inventor： Kazumasa Kamachi ,  Yasuhiro Honma ,  Toshihiro Tanaka ,  Toshio Tsukamoto

IPC: C02F3/28

CPC classification number: C02F3/2846 ,  C02F1/722 ,  C02F1/76 ,  C02F1/78 ,  C02F2101/101 ,  C02F2303/12 ,  C02F2305/06 ,  C12M21/04 ,  C12M23/36 ,  C12M45/06 ,  C12M47/18 ,  Y02E50/343 ,  Y10S210/916

Abstract: A method and apparatus for the anaerobic methane fermentation treatment of a wastewater containing a sulfur compound. An oxidizing agent is added to an organic wastewater to oxidize the sulfur compound contained therein to molecular sulfur before the anaerobic treatment step. The wastewater is then introduced into the anaerobic treatment step for the methane fermentation treatment thereof. The amount of the oxidizing agent to be added to the wastewater is controlled using as an indicator the concentration of the residual oxidizing agent in the water flowing into the anaerobic treatment step and/or the concentration of hydrogen sulfide in a biogas generated. The oxidizing agent may be ozone, hydrogen peroxide, sodium hypochlorite or a bromine based oxidizing agent. When the concentration of hydrogen sulfide in a biogas generated in the anaerobic treatment step is used as said indicator, the oxidizing agent may be suitably added such that the concentration of hydrogen sulfide is 3% or less.

Abstract translation: 一种含有硫化合物的废水的厌氧甲烷发酵处理方法和装置。 在厌氧处理步骤之前，将氧化剂加入到有机废水中以将其中所含的硫化合物氧化成分子硫。 然后将废水引入用于甲烷发酵处理的厌氧处理步骤。 使用作为指标控制流入厌氧处理工序的水中的残留氧化剂的浓度和/或生成的沼气中的硫化氢浓度来控制添加到废水中的氧化剂的量。 氧化剂可以是臭氧，过氧化氢，次氯酸钠或溴系氧化剂。 当在厌氧处理步骤中产生的沼气中的硫化氢浓度用作所述指示剂时，可以适当地加入氧化剂，使得硫化氢的浓度为3％以下。

公开(公告)号：US20060220100A1

公开(公告)日：2006-10-05

申请号：US11415129

申请日：2006-05-02

Applicant: Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

Inventor： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC: H01L29/788

CPC classification number: G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

Abstract translation: 半导体器件包括多个非易失性存储单元（1）。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。 第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。 第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

公开(公告)号：US07110320B2

公开(公告)日：2006-09-19

申请号：US10812080

申请日：2004-03-30

Applicant: Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

Inventor： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

IPC: G11C7/00

CPC classification number: G11C16/0416 ,  G11C8/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

公开(公告)号：US20060196835A1

公开(公告)日：2006-09-07

申请号：US10543930

申请日：2004-01-20

Applicant: Kazuaki Shimamura ,  Toshihiro Tanaka

Inventor： Kazuaki Shimamura ,  Toshihiro Tanaka

IPC: C02F1/52

CPC classification number: C02F1/52 ,  B01D9/0036 ,  B01D9/005 ,  B01D9/0059 ,  C02F1/38 ,  C02F1/66 ,  C02F2101/101 ,  C02F2101/105 ,  C02F2101/14

Abstract: It is an object of the present invention to improve the phosphorus recovery rate in a method and apparatus for removing ions to be removed in a liquid to be treated by crystallizing out crystal particles of a poorly soluble salt of the ions to be removed in the liquid to be treated in a crystallization reaction tank. As one means for attaining this object, in one embodiment of the present invention there is provided a method for removing ions to be removed in a liquid to be treated by crystallizing out crystal particles of a poorly soluble salt of the ions to be removed in the liquid to be treated in a crystallization reaction tank, which comprises adding a chemical agent required for the crystallization reaction into a part of a treated liquid flowing out from the crystallization reaction tank and dissolving the chemical agent therein, and supplying the resulting solution into the crystallization reaction tank as a circulating liquid, wherein the liquid to be treated and the circulating liquid are introduced into the crystallization reaction tank tangentially to a transverse section of the crystallization reaction tank.

Abstract translation: 本发明的目的是提高在待处理液体中除去要除去的离子的方法和装置中的磷回收率，该方法和装置通过在液体中析出待除去的离子的难溶性盐的结晶颗粒， 在结晶反应槽中进行处理。 作为实现该目的的手段之一，在本发明的一个实施方案中，提供了一种通过将待除去的离子的难溶性盐的结晶颗粒结晶化而除去待处理液体中待除去的离子的方法 在结晶反应槽中处理的液体，其包括将结晶反应所需的化学试剂加入到从结晶反应罐中流出的处理液的一部分中并将其中的化学试剂溶解，并将所得溶液供给到结晶 反应罐作为循环液体，其中待处理液体和循环液体与结晶反应罐的横截面切向地引入结晶反应罐中。