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Patent Agency Ranking
公开(公告)号：US09832873B2
公开(公告)日：2017-11-28
申请号：US15426062
申请日：2017-02-07
Applicant: Unimicron Technology Corp.
Inventor： Shu-Sheng Chiang , Ming-Hao Wu , Wei-Ming Cheng
CPC classification number: H05K1/111 , H05K1/0266 , H05K1/0296 , H05K1/0298 , H05K1/09 , H05K1/115 , H05K3/0047 , H05K3/0073 , H05K3/4038 , H05K3/4092 , H05K3/4644 , H05K3/4697 , H05K2201/09036 , H05K2201/094 , H05K2201/09563 , H05K2201/09781 , H05K2203/0376 , H05K2203/163
Abstract: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening connecting the cavity and exposing a portion of the first patterned circuit layer. A hole diameter of the opening is smaller than a hole diameter of cavity. A height difference is between an inner surface of the inner dielectric layer exposed by the cavity and a top surface of the first patterned circuit layer exposed by the opening.
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公开(公告)号：US09609746B1
公开(公告)日：2017-03-28
申请号：US15011649
申请日：2016-01-31
Applicant: Unimicron Technology Corp.
Inventor： Shu-Sheng Chiang , Ming-Hao Wu , Wei-Ming Cheng
CPC classification number: H05K1/111 , H05K1/0266 , H05K1/0296 , H05K1/0298 , H05K1/09 , H05K1/115 , H05K3/0047 , H05K3/0073 , H05K3/4038 , H05K3/4092 , H05K3/4644 , H05K3/4697 , H05K2201/09036 , H05K2201/094 , H05K2201/09563 , H05K2201/09781 , H05K2203/0376 , H05K2203/163
Abstract: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening connecting the cavity and exposing a portion of the first patterned circuit layer. A hole diameter of the opening is smaller than a hole diameter of cavity. A height difference is between an inner surface of the inner dielectric layer exposed by the cavity and a top surface of the first patterned circuit layer exposed by the opening.
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公开(公告)号：US09237643B2
公开(公告)日：2016-01-12
申请号：US13726405
申请日：2012-12-24
Applicant: Unimicron Technology Corp.
Inventor： Tsung-Yuan Chen , Shu-Sheng Chiang , David C. H. Cheng
CPC classification number: H05K1/02 , H05K1/0265 , H05K1/0298 , H05K1/115 , H05K3/045 , H05K3/107 , H05K3/426 , H05K3/465 , H05K2201/0352 , H05K2201/09736 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155
Abstract: A circuit board structure including a dielectric layer, a fine circuit pattern and a patterned conductive layer is provided, wherein the fine circuit pattern is embedded in a surface of the dielectric layer, and the patterned conductive layer is disposed on another surface of the dielectric layer and protrudes therefrom.
Abstract translation: 提供了包括电介质层，精细电路图案和图案化导电层的电路板结构，其中微电路图案嵌入在电介质层的表面中，并且图案化导电层设置在电介质层的另一表面上 并从其突出。
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公开(公告)号：US20140174804A1
公开(公告)日：2014-06-26
申请号：US13726230
申请日：2012-12-24
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： Tzyy-Jang Tseng , Shu-Sheng Chiang , Tsung-Yuan Chen , Shih-Lian Cheng
CPC classification number: H05K3/007 , H01L23/5389 , H01L24/19 , H01L2924/12042 , H05K1/18 , H05K1/183 , H05K1/185 , H05K3/0011 , H05K3/06 , H05K3/30 , H05K3/423 , H05K3/465 , H05K2203/0723 , H05K2203/1469 , Y10T29/4913 , H01L2924/00
Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is formed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed. Moreover, the electrical device package structure is also provided.
Abstract translation: 提供了包括以下步骤的电气设备的包装方法。 提供了包括基板和第一导电图案的电路板。 具有电极的电气装置设置在电路板上。 电介质层形成在电路板上以覆盖电气设备，电极和第一导电图案，其中通过第一导电图案在电介质层中形成第一凹陷图案。 图案化电介质层以形成与通孔连接并暴露电极的通孔和第二凹陷图案。 导电材料填充在通孔和第二凹陷图案中以在通孔中形成导电通孔，并且在第二凹陷图案中填充第二导电图案。 去除衬底。 此外，还提供了电气装置封装结构。
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公开(公告)号：US20130105202A1
公开(公告)日：2013-05-02
申请号：US13726405
申请日：2012-12-24
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： Tsung-Yuan Chen , Shu-Sheng Chiang , David C. H. Cheng
CPC classification number: H05K1/02 , H05K1/0265 , H05K1/0298 , H05K1/115 , H05K3/045 , H05K3/107 , H05K3/426 , H05K3/465 , H05K2201/0352 , H05K2201/09736 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155
Abstract: A circuit board structure including a dielectric layer, a fine circuit pattern and a patterned conductive layer is provided, wherein the fine circuit pattern is embedded in a surface of the dielectric layer, and the patterned conductive layer is disposed on another surface of the dielectric layer and protrudes therefrom.
Abstract translation: 提供了包括电介质层，精细电路图案和图案化导电层的电路板结构，其中微电路图案嵌入在电介质层的表面中，并且图案化导电层设置在电介质层的另一表面上 并从其突出。
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