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    CIRCUIT BOARD
    3.
    发明申请
    CIRCUIT BOARD 审中-公开
    电路板

    公开(公告)号：US20130206467A1

    公开(公告)日：2013-08-15

    申请号：US13846875

    申请日：2013-03-18

    Applicant: UNIMICRON TECHNOLOGY CORP.

    Inventor： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

    IPC: H05K3/06 ,  H05K1/02

    CPC classification number: H05K3/06 ,  H05K1/0298 ,  H05K3/465 ,  H05K2201/0347 ,  Y10T29/49126 ,  Y10T29/49165

    Abstract: A circuit board includes a circuit substrate, a first dielectric layer, a first conductive layer, a second conductive layer and a second dielectric layer. The circuit substrate has a first surface and a first circuit layer. The first dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The first dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit layer, and an intaglio pattern. The first conductive layer is disposed in the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via. The second conductive layer is electrically connected to the first circuit layer via the first conductive layer. The second dielectric layer is disposed on the first dielectric layer and covers the second conductive layer and the second surface of the first dielectric layer.

    Abstract translation: 电路板包括电路基板，第一介电层，第一导电层，第二导电层和第二介电层。 电路基板具有第一表面和第一电路层。 第一电介质层设置在电路基板上并覆盖第一表面和第一电路层。 第一电介质层具有第二表面，至少从第二表面延伸到第一电路层的盲孔以及凹版图案。 第一导电层设置在盲孔中。 第二导电层设置在凹版图案和盲孔中。 第二导电层经由第一导电层电连接到第一电路层。 第二电介质层设置在第一电介质层上并覆盖第二导电层和第一介电层的第二表面。

    Method of fabricating an electrical device package structure
    4.
    发明授权
    Method of fabricating an electrical device package structure 有权

    公开(公告)号：US10271433B2

    公开(公告)日：2019-04-23

    申请号：US14855404

    申请日：2015-09-16

    Applicant: Unimicron Technology Corp.

    Inventor： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen ,  Shih-Lian Cheng

    IPC: H05K3/30 ,  H05K3/00 ,  H05K1/18 ,  H01L23/538 ,  H01L23/00 ,  H05K3/06 ,  H05K3/42 ,  H05K3/46

    Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is formed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed.

    Embedded chip package structure
    5.
    发明授权
    Embedded chip package structure 有权
    嵌入式芯片封装结构

    公开(公告)号：US09324664B2

    公开(公告)日：2016-04-26

    申请号：US13773647

    申请日：2013-02-22

    Applicant: Unimicron Technology Corp.

    Inventor： Tsung-Yuan Chen ,  Wei-Ming Cheng

    IPC: H01L23/48 ,  H01L23/60 ,  H01L23/00

    CPC classification number: H01L23/60 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/19 ,  H01L2224/2518 ,  H01L2924/0002 ,  H01L2924/3511 ,  H01L2924/00

    Abstract: An embedded chip package structure including a core layer, a chip, a first circuit layer and a second circuit layer is provided. The core layer includes a first surface, a second surface opposite to each other and a chip container passing through the first surface and the second surface. The chip is disposed in the chip container. The chip includes an active surface and a protrusion and a top surface of the protrusion is a part of the active surface. The first circuit layer is disposed on the first surface and electrically connected to the core layer and the chip. The first circuit layer has a through hole. The protrusion of the chip is situated within the through hole, and the top surface of the protrusion is exposed to receive an external signal. The second circuit layer is disposed on the second surface and electrically connected to the core layer.

    Abstract translation: 提供了包括核心层，芯片，第一电路层和第二电路层的嵌入式芯片封装结构。 芯层包括第一表面，彼此相对的第二表面和穿过第一表面和第二表面的芯片容器。 芯片设置在芯片容器中。 芯片包括有源表面和突起，突起的顶表面是活性表面的一部分。 第一电路层设置在第一表面上并与芯层和芯片电连接。 第一电路层具有通孔。 芯片的突出部位于通孔内，突出部的顶面露出来接收外部信号。 第二电路层设置在第二表面上并与芯层电连接。

    EMBEDDED CHIP PACKAGE STRUCTURE
    8.
    发明申请
    EMBEDDED CHIP PACKAGE STRUCTURE 有权
    嵌入式芯片包装结构

    公开(公告)号：US20140239463A1

    公开(公告)日：2014-08-28

    申请号：US13773647

    申请日：2013-02-22

    Applicant: UNIMICRON TECHNOLOGY CORP.

    Inventor： Tsung-Yuan Chen ,  Wei-Ming Cheng

    IPC: H01L23/60

    CPC classification number: H01L23/60 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/19 ,  H01L2224/2518 ,  H01L2924/0002 ,  H01L2924/3511 ,  H01L2924/00

    Abstract: An embedded chip package structure including a core layer, a chip, a first circuit layer and a second circuit layer is provided. The core layer includes a first surface, a second surface opposite to each other and a chip container passing through the first surface and the second surface. The chip is disposed in the chip container. The chip includes an active surface and a protrusion and a top surface of the protrusion is a part of the active surface. The first circuit layer is disposed on the first surface and electrically connected to the core layer and the chip. The first circuit layer has a through hole. The protrusion of the chip is situated within the through hole, and the top surface of the protrusion is exposed to receive an external signal. The second circuit layer is disposed on the second surface and electrically connected to the core layer.

    Abstract translation: 提供了包括核心层，芯片，第一电路层和第二电路层的嵌入式芯片封装结构。 芯层包括第一表面，彼此相对的第二表面和穿过第一表面和第二表面的芯片容器。 芯片设置在芯片容器中。 芯片包括有源表面和突起，突起的顶表面是活性表面的一部分。 第一电路层设置在第一表面上并与芯层和芯片电连接。 第一电路层具有通孔。 芯片的突出部位于通孔内，突出部的顶面露出来接收外部信号。 第二电路层设置在第二表面上并与芯层电连接。

    ELECTRICAL DEVICE PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME
    9.
    发明申请
    ELECTRICAL DEVICE PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
    电气设备包装结构及其制造方法

    公开(公告)号：US20140174804A1

    公开(公告)日：2014-06-26

    申请号：US13726230

    申请日：2012-12-24

    Applicant: UNIMICRON TECHNOLOGY CORP.

    Inventor： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen ,  Shih-Lian Cheng

    IPC: H05K1/18 ,  H05K3/30

    CPC classification number: H05K3/007 ,  H01L23/5389 ,  H01L24/19 ,  H01L2924/12042 ,  H05K1/18 ,  H05K1/183 ,  H05K1/185 ,  H05K3/0011 ,  H05K3/06 ,  H05K3/30 ,  H05K3/423 ,  H05K3/465 ,  H05K2203/0723 ,  H05K2203/1469 ,  Y10T29/4913 ,  H01L2924/00

    Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is formed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed. Moreover, the electrical device package structure is also provided.

    Abstract translation: 提供了包括以下步骤的电气设备的包装方法。 提供了包括基板和第一导电图案的电路板。 具有电极的电气装置设置在电路板上。 电介质层形成在电路板上以覆盖电气设备，电极和第一导电图案，其中通过第一导电图案在电介质层中形成第一凹陷图案。 图案化电介质层以形成与通孔连接并暴露电极的通孔和第二凹陷图案。 导电材料填充在通孔和第二凹陷图案中以在通孔中形成导电通孔，并且在第二凹陷图案中填充第二导电图案。 去除衬底。 此外，还提供了电气装置封装结构。

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