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    Manufacturing method for a shallow trench isolation
    11.
    发明授权
    Manufacturing method for a shallow trench isolation 有权
    浅沟槽隔离的制造方法

    公开(公告)号：US09012300B2

    公开(公告)日：2015-04-21

    申请号：US13633104

    申请日：2012-10-01

    Applicant: United Microelectronics Corp.

    Inventor： Wu-Sian Sie ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Yu-Ting Li ,  Wei-Che Tsao ,  Yen-Ming Chen ,  Chun-Hsiung Wang ,  Chia-Lin Hsu

    IPC: H01L21/76 ,  H01L21/762

    CPC classification number: H01L21/76232 ,  H01L21/76229

    Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.

    Abstract translation: 浅沟槽隔离的制造方法。 首先，提供基板，在基板上顺序地形成硬掩模层和图案化的光致抗蚀剂层，然后通过蚀刻工艺在基板中形成至少一个沟槽，去除硬掩模层。 然后，至少在沟槽中形成填料，然后对填料进行平面化处理。 由于仅在填料上进行平坦化处理，所以可以有效地避免凹陷现象。

    Method of forming an isolation structure
    13.
    发明授权
    Method of forming an isolation structure 有权
    形成隔离结构的方法

    公开(公告)号：US08709901B1

    公开(公告)日：2014-04-29

    申请号：US13864277

    申请日：2013-04-17

    Applicant: United Microelectronics Corp.

    Inventor： Chia-Lung Chang ,  Wu-Sian Sie ,  Jei-Ming Chen ,  Wen-Yi Teng ,  Chih-Chien Liu ,  Jui-Min Lee ,  Chih-Hsun Lin

    IPC: H01L21/336

    CPC classification number: H01L21/76224 ,  H01L21/31053 ,  H01L21/32105

    Abstract: The present invention relates to a method of forming an isolation structure, in which, a trench is formed in a substrate through a hard mask, and deposition, etch back, deposition, planarization, and etch back are performed in the order to form an isolation material layer of the isolation structure after the hard mask is removed. A silicon layer may be formed to cover the trench and original surface of the substrate before the former deposition, or to cover a part of the trench and original surface of the substrate after the former etch back and before the later deposition, to serve as a stop layer for the planarization process. Voids existing within the isolation material layer can be exposed or removed by partially etching the isolation material layer by the former etch back. The later deposition can be performed with a less aspect ratio to avoid forming voids.

    Abstract translation: 本发明涉及一种形成隔离结构的方法，其中通过硬掩模在衬底中形成沟槽，并且进行沉积，回蚀刻，沉积，平坦化和回蚀以形成隔离 去除硬掩模后隔离结构的材料层。 可以形成硅层以在前一次沉积之前覆盖衬底的沟槽和原始表面，或者在前面的回蚀刻和稍后的沉积之前覆盖衬底的一部分沟槽和原始表面，以用作 停止层进行平面化处理。 存在于隔离材料层内的空隙可以通过由前面的回蚀部分蚀刻隔离材料层而被暴露或去除。 可以以较小的纵横比进行后续沉积以避免形成空隙。

    Method of forming target patterns
    15.
    发明授权
    Method of forming target patterns 有权
    形成目标图案的方法

    公开(公告)号：US09466535B2

    公开(公告)日：2016-10-11

    申请号：US14636940

    申请日：2015-03-03

    Applicant: United Microelectronics Corp.

    Inventor： Po-Cheng Huang ,  Kun-Ju Li ,  Yu-Ting Li ,  Chih-Hsun Lin

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/033 ,  H01L21/306

    CPC classification number: H01L21/823437 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/6681

    Abstract: A method of forming target patterns is disclosed. A substrate with multiple fins is provided. A plurality of mask patterns is formed across the fins and in at least a part of non-target areas. Target patterns are formed respectively in trenches between the mask patterns. The mask patterns are removed. With the disclosed method, the target patterns can be formed with substantially equal thickness. In the case that the target patterns are dummy gates, the conventional defects such as dummy gate residues or gate trench widening caused by uneven thicknesses are not observed upon the dummy gate removal step.

    Abstract translation: 公开了形成目标图案的方法。 提供具有多个散热片的基板。 在鳍片和非目标区域的至少一部分中形成多个掩模图案。 目标图案分别形成在掩模图案之间的沟槽中。 去除掩模图案。 利用所公开的方法，可以以基本相等的厚度形成目标图案。 在目标图案是伪栅极的情况下，在虚拟栅极去除步骤中没有观察到由不均匀厚度引起的诸如伪栅极残留或栅极沟槽加宽的常规缺陷。

    METHOD OF FORMING TARGET PATTERNS
    16.
    发明申请
    METHOD OF FORMING TARGET PATTERNS 有权
    形成目标图案的方法

    公开(公告)号：US20160260637A1

    公开(公告)日：2016-09-08

    申请号：US14636940

    申请日：2015-03-03

    Applicant: United Microelectronics Corp.

    Inventor： Po-Cheng Huang ,  Kun-Ju Li ,  Yu-Ting Li ,  Chih-Hsun Lin

    IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/306 ,  H01L29/66

    CPC classification number: H01L21/823437 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/6681

    Abstract: A method of forming target patterns is disclosed. A substrate with multiple fins is provided. A plurality of mask patterns is formed across the fins and in at least a part of non-target areas. Target patterns are formed respectively in trenches between the mask patterns. The mask patterns are removed. With the disclosed method, the target patterns can be formed with substantially equal thickness. In the case that the target patterns are dummy gates, the conventional defects such as dummy gate residues or gate trench widening caused by uneven thicknesses are not observed upon the dummy gate removal step.

    Abstract translation: 公开了形成目标图案的方法。 提供具有多个散热片的基板。 在鳍片和非目标区域的至少一部分中形成多个掩模图案。 目标图案分别形成在掩模图案之间的沟槽中。 去除掩模图案。 利用所公开的方法，可以以基本相等的厚度形成目标图案。 在目标图案是伪栅极的情况下，在虚拟栅极去除步骤中没有观察到由不均匀厚度引起的诸如伪栅极残留或栅极沟槽加宽的常规缺陷。

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