公开(公告)号：US09466480B2

公开(公告)日：2016-10-11

申请号：US14532015

申请日：2014-11-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Chueh-Yang Liu ,  Neng-Hui Yang

IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/02334 ,  H01L21/0206 ,  H01L21/02181 ,  H01L21/02307 ,  H01L21/28211 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A cleaning process for oxide includes the following step. A substrate having a first area and a second area is provided. A first oxide layer is formed on the substrate of the first area and the second area. An ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2) containing process is performed on the first oxide layer of the first area and the second area. A photoresist layer covers the first oxide layer of the first area while exposing the first oxide layer of the second area. The first oxide layer of the second area is removed. The photoresist layer is then removed.

Abstract translation: 氧化物的清洗方法包括以下步骤。 提供具有第一区域和第二区域的衬底。 在第一区域和第二区域的基板上形成第一氧化物层。 在第一区域和第二区域的第一氧化物层上进行含有氢氧化铵（NH 4 OH）和过氧化氢（H 2 O 2）的工艺。 光致抗蚀剂层覆盖第一区域的第一氧化物层，同时暴露第二区域的第一氧化物层。 去除第二区域的第一氧化物层。 然后除去光致抗蚀剂层。

公开(公告)号：US10128366B2

公开(公告)日：2018-11-13

申请号：US15890303

申请日：2018-02-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Kuan Hsuan Ku ,  I-Cheng Hu ,  Chueh-Yang Liu ,  Shui-Yen Lu ,  Yu Shu Lin ,  Chun Yao Yang ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: H01L21/00 ,  H01L29/78 ,  H01L21/225 ,  H01L29/06 ,  H01L21/768 ,  H01L21/311 ,  H01L29/417 ,  H01L29/165 ,  H01L27/092

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.

公开(公告)号：US20180158943A1

公开(公告)日：2018-06-07

申请号：US15890303

申请日：2018-02-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Kuan Hsuan KU ,  I-Cheng Hu ,  Chueh-Yang Liu ,  Shui-Yen Lu ,  Yu Shu LIN ,  Chun Yao YANG ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/165 ,  H01L29/06 ,  H01L21/225 ,  H01L21/768 ,  H01L21/311 ,  H01L27/092

CPC classification number: H01L29/78 ,  H01L21/31144 ,  H01L21/76877 ,  H01L27/0922 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.

公开(公告)号：US20180122707A1

公开(公告)日：2018-05-03

申请号：US15339949

申请日：2016-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Wen-Jiun Shen ,  Yu-Ren Wang

IPC: H01L21/8238 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66 ,  H01L21/311 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/6653 ,  H01L29/7848 ,  H01L29/785

Abstract: The present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a NMOS region and a PMOS region defined thereon, next, a gate structure is formed on the substrate within the NMOS region, and a disposal spacer is formed on two sides of the gate structure, afterwards, a mask layer is formed on the PMOS region to expose the NMOS region, next, a recess is formed on two sides of the gate structure spaced from the gate structure by the disposal spacer within the NMOS region, the disposal spacer is then removed after the recess is formed, and an epitaxial layer is formed into the recess.

公开(公告)号：US20170330742A1

公开(公告)日：2017-11-16

申请号：US15636660

申请日：2017-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L21/0206 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes fin shaped structures and a recessed insulating layer. The fin shaped structures are disposed on a substrate. The recessed insulating layer covers a bottom portion of each of the fin shaped structures to expose a top portion of each of the fin shaped structures. The recessed insulating layer has a curve surface and a wicking structure is defined between a peak and a bottom of the curve surface. The wicking structure is disposed between the fin shaped structures and has a height being about 1/12 to 1/10 of a height of the top portion of the fin shaped structures.

公开(公告)号：US09748111B2

公开(公告)日：2017-08-29

申请号：US15012821

申请日：2016-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L21/461 ,  H01L21/321 ,  H01L29/66 ,  H01L21/3205 ,  H01L21/283 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L21/3212 ,  H01L21/02065 ,  H01L21/02074 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/283 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/32055 ,  H01L21/32115 ,  H01L29/66795

Abstract: A method for fabricating a semiconductor structure includes following steps. First, a first layer, a second layer and a third layer are sequentially formed on the substrate. The second layer is conformally disposed on the top surface of the first layer. The second layer and the first layer have different compositions, and the third layer and the second layer also have different compositions. Then, a planarizing process is performed on the third layer until portions of the second layer are exposed. Afterwards, hydrofluoric acid and aqueous oxidant are concurrently or sequentially provided to the remaining second and third layers. Finally, an etch back process is carried out to remove all the second layer and portions of the first layer.

公开(公告)号：US09741572B1

公开(公告)日：2017-08-22

申请号：US15049152

申请日：2016-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chueh-Yang Liu ,  Chun-Wei Yu ,  Yu-Ying Lin ,  Yu-Ren Wang

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28185 ,  H01L21/28167 ,  H01L21/823462 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of forming an oxide layer is provided in the present invention. The method includes the following steps. A first oxide layer is formed on a semiconductor substrate, and a quality enhancement process is then performed to etch the first oxide layer and densify the first oxide layer at the same time for forming a second oxide layer. The first oxide layer is etched and densified at the same time by a mixture of dilute hydrofluoric acid (DHF) and hydrogen peroxide (H2O2) in the quality enhancement process. The thickness of the second oxide layer may be reduced and the quality of the second oxide layer may be enhanced by the quality enhancement process at the same time.

公开(公告)号：US20160172190A1

公开(公告)日：2016-06-16

申请号：US14571249

申请日：2014-12-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Lin Shih ,  Chueh-Yang Liu ,  Shao-Wei Wang ,  Che-Hung Huang ,  Po-Hua Jen ,  Shih-Hao Su

IPC: H01L21/02 ,  H01L21/283

CPC classification number: H01L21/28211 ,  H01L21/76224 ,  H01L21/823462

Abstract: A gate oxide formation process includes the following steps. A first gate oxide layer is formed on a substrate. The first gate oxide layer is thinned to a first predetermined thickness. The first gate oxide layer is then thickened to a second predetermined thickness, to thereby form a second gate oxide layer.

Abstract translation: 栅极氧化物形成工艺包括以下步骤。 在基板上形成第一栅氧化层。 第一栅极氧化物层被薄化到第一预定厚度。 然后将第一栅极氧化物层增厚至第二预定厚度，从而形成第二栅极氧化物层。

公开(公告)号：US20160126091A1

公开(公告)日：2016-05-05

申请号：US14532015

申请日：2014-11-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Chueh-Yang Liu ,  Neng-Hui Yang

IPC: H01L21/02 ,  H01L21/311

CPC classification number: H01L21/02334 ,  H01L21/0206 ,  H01L21/02181 ,  H01L21/02307 ,  H01L21/28211 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A cleaning process for oxide includes the following step. A substrate having a first area and a second area is provided. A first oxide layer is formed on the substrate of the first area and the second area. An ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2) containing process is performed on the first oxide layer of the first area and the second area. A photoresist layer covers the first oxide layer of the first area while exposing the first oxide layer of the second area. The first oxide layer of the second area is removed. The photoresist layer is then removed.

Abstract translation: 氧化物的清洗方法包括以下步骤。 提供具有第一区域和第二区域的衬底。 在第一区域和第二区域的基板上形成第一氧化物层。 在第一区域和第二区域的第一氧化物层上进行含有氢氧化铵（NH 4 OH）和过氧化氢（H 2 O 2）的工艺。 光致抗蚀剂层覆盖第一区域的第一氧化物层，同时暴露第二区域的第一氧化物层。 去除第二区域的第一氧化物层。 然后除去光致抗蚀剂层。

公开(公告)号：US10651174B2

公开(公告)日：2020-05-12

申请号：US16412337

申请日：2019-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/51

Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.