公开(公告)号：US10460925B2

公开(公告)日：2019-10-29

申请号：US15639381

申请日：2017-06-30

Applicant: United Microelectronics Corp.

Inventor： Hsu Ting ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Keng-Jen Lin ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L21/311 ,  H01L29/66

Abstract: A method for processing a semiconductor device is provided. The semiconductor device includes a protruding structure on a substrate, the protruding structure having a nitride spacer at a sidewall, and an epitaxial layer is formed in the substrate adjacent to the protruding structure. The method includes removing the nitride spacer on the protruding structure. Then, a dilute hydrofluoric (DHF) cleaning process is performed over the substrate, wherein a top surficial portion of the epitaxial layer is removed. A standard clean (SC) process is performed over the substrate, wherein a native oxide layer is formed on an expose surface of the epitaxial layer.

公开(公告)号：US10366991B1

公开(公告)日：2019-07-30

申请号：US15880492

申请日：2018-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Yu-Ying Lin ,  Yen-Hsing Chen ,  Chun-Jen Chen ,  Chun-Wei Yu ,  Keng-Jen Lin ,  Yu-Ren Wang

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.

公开(公告)号：US20180096995A1

公开(公告)日：2018-04-05

申请号：US15284552

申请日：2016-10-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/517

Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.

公开(公告)号：US09871113B2

公开(公告)日：2018-01-16

申请号：US15064275

申请日：2016-03-08

Applicant: United Microelectronics Corp.

Inventor： Chun-Wei Yu ,  Kuang-Hsiu Chen ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L21/266 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/66492 ,  H01L21/02164 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/2652 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66636

Abstract: A semiconductor process including the following steps is provided. An epitaxial layer is formed on a substrate. An oxide layer is formed on the epitaxial layer, wherein the oxide layer includes a chemical oxide layer, a high-temperature oxide (HTO) layer or a surface modification oxide layer. An ion implant process is performed to the epitaxial layer to form a doped region in the epitaxial layer. The oxide layer is removed by using a diluted hydrofluoric acid (DHF) solution after performing the ion implant process, wherein a volume ratio of water to a hydrofluoric acid (HF) in the DHF solution is 200:1 to 1000:1.

公开(公告)号：US20230369460A1

公开(公告)日：2023-11-16

申请号：US17835977

申请日：2022-06-09

Applicant: United Microelectronics Corp.

Inventor： Kuang-Hsiu Chen ,  Wei-Chung Sun ,  Chao Nan Chen ,  Chun-Wei Yu ,  Kuan Hsuan Ku ,  Shao-Wei Wang

IPC: H01L29/66

CPC classification number: H01L29/66636 ,  H01L29/66575 ,  H01L29/66446 ,  H01L29/66795

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes the following. A gate structure is formed on a substrate. A tilt implanting process is performed to implant group IV elements into the substrate to form a doped region, and the doped region is located on two sides of the gate structure and partially located under the gate structure. A part of the substrate on two sides of the gate structure is removed to form a first recess. A cleaning process is performed on the surface of the first recess. A wet etching process is performed on the first recess to form a second recess. A semiconductor layer is formed in the second recess.

公开(公告)号：US20190221562A1

公开(公告)日：2019-07-18

申请号：US15880492

申请日：2018-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Yu-Ying Lin ,  Yen-Hsing Chen ,  Chun-Jen Chen ,  Chun-Wei Yu ,  Keng-Jen Lin ,  Yu-Ren Wang

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66545

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.

公开(公告)号：US20180323058A1

公开(公告)日：2018-11-08

申请号：US15590004

申请日：2017-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L21/02 ,  C09G1/02 ,  C08K5/42 ,  C08K5/14

CPC classification number: H01L21/02074 ,  H01L21/02065 ,  H01L21/32115 ,  H01L29/00

Abstract: A method for post chemical mechanical polishing clean is provided in the present invention, which include the steps of providing a substrate, performing a chemical mechanical polishing process, and performing a plurality of cleaning processes sequentially substrate using solutions of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) with different ratios and at different temperatures.

公开(公告)号：US09960084B1

公开(公告)日：2018-05-01

申请号：US15339949

申请日：2016-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Wen-Jiun Shen ,  Yu-Ren Wang

IPC: H01L21/8238 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66 ,  H01L21/311 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/6653 ,  H01L29/7848 ,  H01L29/785

Abstract: The present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a NMOS region and a PMOS region defined thereon, next, a gate structure is formed on the substrate within the NMOS region, and a disposal spacer is formed on two sides of the gate structure, afterwards, a mask layer is formed on the PMOS region to expose the NMOS region, next, a recess is formed on two sides of the gate structure spaced from the gate structure by the disposal spacer within the NMOS region, the disposal spacer is then removed after the recess is formed, and an epitaxial layer is formed into the recess.

公开(公告)号：US20170309485A1

公开(公告)日：2017-10-26

申请号：US15137010

申请日：2016-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Chun-Wei Yu ,  Kuang-Hsiu Chen ,  Yi-Liang Ye ,  Hsu Ting ,  Neng-Hui Yang

IPC: H01L21/268 ,  H01L21/687 ,  H01L21/67 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/2686 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/67115 ,  H01L21/68785 ,  H01L29/0847 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7834

Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.

公开(公告)号：US20170263730A1

公开(公告)日：2017-09-14

申请号：US15064275

申请日：2016-03-08

Applicant: United Microelectronics Corp.

Inventor： Chun-Wei Yu ,  Kuang-Hsiu Chen ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L29/66 ,  H01L21/266 ,  H01L29/49 ,  H01L21/02

CPC classification number: H01L29/66492 ,  H01L21/02164 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/2652 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66636

Abstract: A semiconductor process including the following steps is provided. An epitaxial layer is formed on a substrate. An oxide layer is formed on the epitaxial layer, wherein the oxide layer includes a chemical oxide layer, a high-temperature oxide (HTO) layer or a surface modification oxide layer. An ion implant process is performed to the epitaxial layer to form a doped region in the epitaxial layer. The oxide layer is removed by using a diluted hydrofluoric acid (DHF) solution after performing the ion implant process, wherein a volume ratio of water to a hydrofluoric acid (HF) in the DHF solution is 200:1 to 1000:1.