公开(公告)号：US09361097B2

公开(公告)日：2016-06-07

申请号：US14088565

申请日：2013-11-25

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean

IPC: G06F9/28 ,  G06F9/30

CPC classification number: G06F9/30178 ,  G06F9/26 ,  G06F9/268 ,  G06F9/28 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/3802

Abstract: A microprocessor includes one or more memories configured to hold microcode instructions, wherein at least a portion of the microcode instructions are compressed. The microprocessor also includes a decompression unit configured to decompress the compressed microcode instructions after being fetched from the one or more memories and before being executed. A method includes receiving from a memory a first N-bit wide microcode word, determining whether or not a predetermined portion of the first N-bit wide microcode word is a predetermined value, if the predetermined portion is not the predetermined value, decompressing the first N-bit wide microcode word to generate an M-bit wide microcode word, and if the predetermined portion is the predetermined value, receiving from the memory a second N-bit wide microcode word and joining portions of the first and second N-bit wide microcode words to generate the M-bit wide microcode word.

Abstract translation: 微处理器包括被配置为保持微代码指令的一个或多个存储器，其中至少一部分微代码指令被压缩。 该微处理器还包括一个解压缩单元，配置成在从一个或多个存储器中取出并在被执行之前解压缩压缩的微代码指令。 一种方法包括从存储器接收第一N位宽的微码字，如果预定部分不是预定值，则确定第一N位宽微码字的预定部分是否是预定值，解压缩第一 N位宽的微码字以产生M位宽的微码字，并且如果预定部分是预定值，则从存储器接收第二N位宽的微码字，并将第一和第二N位宽的连接部分 微码字来生成M位宽的微码字。

公开(公告)号：US09330011B2

公开(公告)日：2016-05-03

申请号：US14050757

申请日：2013-10-10

Applicant: VIA Technologies, Inc.

Inventor： Terry Parks

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F12/0875 ,  G06F9/30076 ,  G06F9/30079 ,  G06F9/38 ,  G06F9/3867 ,  G06F9/3897 ,  G06F9/44505

Abstract: A microprocessor includes an instruction cache and a hardware state machine configured to detect a no operation (NOP) slide by counting a continuous sequence of NOP instructions within a stream of instructions fetched from the instruction cache. The microprocessor is configured to suspend execution of the stream of instructions, and transfer control to another routine, in response to detecting the NOP slide.

Abstract translation: 微处理器包括指令高速缓存和配置成通过对从指令高速缓存取出的指令流中的连续NOP指令序列进行计数来检测无操作（NOP）幻灯片的硬件状态机。 微处理器被配置为暂停指令流的执行，并且响应于检测到NOP幻灯片而将控制转移到另一例程。

公开(公告)号：US20150113253A1

公开(公告)日：2015-04-23

申请号：US14088565

申请日：2013-11-25

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean

IPC: G06F9/28

CPC classification number: G06F9/30178 ,  G06F9/26 ,  G06F9/268 ,  G06F9/28 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/3802

Abstract: A microprocessor includes one or more memories configured to hold microcode instructions, wherein at least a portion of the microcode instructions are compressed. The microprocessor also includes a decompression unit configured to decompress the compressed microcode instructions after being fetched from the one or more memories and before being executed. A method includes receiving from a memory a first N-bit wide microcode word, determining whether or not a predetermined portion of the first N-bit wide microcode word is a predetermined value, if the predetermined portion is not the predetermined value, decompressing the first N-bit wide microcode word to generate an M-bit wide microcode word, and if the predetermined portion is the predetermined value, receiving from the memory a second N-bit wide microcode word and joining portions of the first and second N-bit wide microcode words to generate the M-bit wide microcode word.

Abstract translation: 微处理器包括被配置为保持微代码指令的一个或多个存储器，其中至少一部分微代码指令被压缩。 该微处理器还包括一个解压缩单元，配置成在从一个或多个存储器中取出并在被执行之前解压缩压缩的微代码指令。 一种方法包括从存储器接收第一N位宽的微码字，如果预定部分不是预定值，则确定第一N位宽微码字的预定部分是否是预定值，解压缩第一 N位宽的微码字以产生M位宽的微码字，并且如果预定部分是预定值，则从存储器接收第二N位宽的微码字，并将第一和第二N位宽的连接部分 微码字来生成M位宽的微码字。

公开(公告)号：US20150089204A1

公开(公告)日：2015-03-26

申请号：US14050687

申请日：2013-10-10

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Rodney E. Hooker ,  Colin Eddy ,  Terry Parks

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F8/654 ,  G06F9/30181 ,  G06F15/7892 ,  G06F17/5054

Abstract: A microprocessor includes a plurality of dynamically reconfigurable functional units, a fingerprint, and a fingerprint unit. As the plurality of dynamically reconfigurable functional units execute instructions according to a first configuration setting, the fingerprint unit accumulates information about the instructions according to a mathematical operation to generate a result. The microprocessor also includes a reconfiguration unit that reconfigures the plurality of dynamically reconfigurable functional units to execute instructions according to a second configuration setting in response to an indication that the result matches the fingerprint.

Abstract translation: 微处理器包括多个动态可重构功能单元，指纹和指纹单元。 当多个动态可重构功能单元根据第一配置设置执行指令时，指纹单元根据数学运算累加关于指令的信息以产生结果。 微处理器还包括重配置单元，其重新配置多个动态可重配置功能单元，以响应于结果与指纹匹配的指示，根据第二配置设置来执行指令。

公开(公告)号：US08793785B2

公开(公告)日：2014-07-29

申请号：US14053953

申请日：2013-10-15

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Terry Parks

IPC: G06F12/14 ,  G06F21/31 ,  G06F9/30 ,  G06F21/78 ,  G06F21/79 ,  G06F21/71

CPC classification number: G06F12/1408 ,  G06F9/30076 ,  G06F9/30101 ,  G06F21/31 ,  G06F21/71 ,  G06F21/78 ,  G06F21/79

Abstract: A microprocessor includes a model specific register (MSR) having an address, fuses manufactured with a first predetermined value, and a control register. The microprocessor initially loads the first predetermined value from fuses into the control register. The microprocessor also receives a second predetermined value into the control register from system software of a computer system comprising the microprocessor subsequent to initially loading the first predetermined value into the control register. The microprocessor prohibits access to the MSR by an instruction that provides a first password generated by encrypting a function of the first predetermined value and the MSR address with a secret key manufactured into the first instance of the microprocessor and enables access to the MSR by an instruction that provides a second password generated by encrypting the function of the second predetermined value and the MSR address with the secret key.

Abstract translation: 微处理器包括具有地址的型号特定寄存器（MSR），具有第一预定值制造的保险丝和控制寄存器。 微处理器首先将第一预定值从保险丝加载到控制寄存器中。 在最初将第一预定值加载到控制寄存器之后，微处理器还从包括微处理器的计算机系统的系统软件接收第二预定值。 微处理器通过提供通过利用在微处理器的第一实例中制造的秘密密钥加密第一预定值和MSR地址的功能产生的第一密码的指令来禁止对MSR的访问，并使得能够通过指令访问MSR 其提供通过用秘密密钥加密第二预定值的功能和MSR地址产生的第二密码。

公开(公告)号：US09911008B2

公开(公告)日：2018-03-06

申请号：US14884547

申请日：2015-10-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

IPC: G06F21/72 ,  G06F9/30 ,  H04L9/08 ,  G06F21/74 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/60 ,  G06F21/71 ,  H04L9/06

CPC classification number: G06F21/72 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/3017 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/74 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0827 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

Abstract: A microprocessor is provided in which an encrypted program can replace the decryption keys that are used to decrypt sections of the encrypted program. The microprocessor may be decrypting and executing a first section of the encrypted program when it encounters, decrypts, and executes an encrypted store-key instruction to store a new set of decryption keys. After executing the store-key instruction, the microprocessor decrypts and executes a subsequent section of the encrypted program using the new set of decryption keys. On-the-fly key switching may occur numerous times with successive encrypted store-key instructions and successive sets of encrypted instructions.

公开(公告)号：US09898303B2

公开(公告)日：2018-02-20

申请号：US14281585

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks

IPC: G06F12/08 ,  G06F9/38 ,  G06F1/32 ,  G06F12/084 ,  G06F13/24 ,  G06F9/44 ,  G06F13/364 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0875 ,  G06F1/04 ,  G06F1/12 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  H04L9/08 ,  H01L21/66

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of processing cores, a resource shared by the plurality of processing cores, and a hardware semaphore readable and writeable by each of the plurality of processing cores within a non-architectural address space. Each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained. Each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource.

公开(公告)号：US09792121B2

公开(公告)日：2017-10-17

申请号：US14066520

申请日：2013-10-29

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Terry Parks ,  G. Glenn Henry

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3836

Abstract: A microprocessor includes an instruction translation unit that extracts condition information from the IT instruction and fuses the IT instruction with the first IT block instruction. For each instruction of the IT block, the instruction translation unit: determines a respective condition for the IT block instruction using the condition information extracted from the IT instruction and translates the IT block instruction into a microinstruction. The microinstruction includes the respective condition. Execution units conditionally execute the microinstruction based on the respective condition. For each IT block instruction, the instruction translation unit determines a respective state value using the extracted condition information. The state value comprises the lower eight bits of the IT instruction having the lower five bits left-shifted by N-1 bits, where N indicates a position of the IT block instruction in the IT block.

公开(公告)号：US09588572B2

公开(公告)日：2017-03-07

申请号：US14281681

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks

IPC: G06F13/32 ,  G06F1/00 ,  G06F1/32 ,  G06F12/08 ,  G06F13/24 ,  G06F9/44 ,  G06F13/364 ,  G06F9/38 ,  G06F9/30 ,  G06F1/04 ,  G06F1/12

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of processing cores, each comprising a respective interrupt request input and a control unit configured to receive a respective synchronization request from each of the plurality of processing cores. The control unit is configured to generate an interrupt request to all of the plurality of processing cores on their respective interrupt request inputs in response to detecting that the control unit has received the respective synchronization request from all of the plurality of processing cores.

Abstract translation: 微处理器包括多个处理核，每个处理核包括相应的中断请求输入和被配置为从多个处理核中的每一个接收相应的同步请求的控制单元。 控制单元被配置为响应于检测到控制单元已经从所有多个处理核心中接收到相应的同步请求而在其各自的中断请求输入端上产生对所有多个处理核心的中断请求。

公开(公告)号：US09513687B2

公开(公告)日：2016-12-06

申请号：US14281488

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks

IPC: G06F1/12 ,  G06F1/32 ,  G06F1/04 ,  G06F12/08 ,  G06F13/24 ,  G06F9/38 ,  G06F9/30 ,  G06F9/44

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of semiconductor dies, a bus coupling the plurality of semiconductor dies, and a plurality of processing cores. A distinct subset of the processing cores is located on each of the semiconductor dies. Each die comprises a control unit configured to selectively control a respective clock signal to each of the subset of cores of the die. For each core of the subset, in response to the core writing a value to the control unit, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the control unit of the other die. Collectively all of the control units are configured to simultaneously turn on the clock signals to all of the processing cores after the clock signals have been turned off to all of the processing cores.

Abstract translation: 微处理器包括多个半导体管芯，耦合多个半导体管芯的总线以及多个处理核心。 处理核心的不同子集位于每个半导体管芯上。 每个管芯包括控制单元，该控制单元被配置为选择性地将相应的时钟信号控制到芯片的核心子集中的每一个。 对于子集的每个核心，响应于核心向控制单元写入值，控制单元被配置为关闭相应的时钟信号到核心，并将总线上的值写入另一个的控制单元 死。 集中地，所有控制单元被配置为在时钟信号已经被关闭到所有处理核之后同时打开到所有处理核的时钟信号。