公开(公告)号：US20140099759A1

公开(公告)日：2014-04-10

申请号：US14104096

申请日：2013-12-12

申请人： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

发明人： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

IPC分类号： H01L21/8238

CPC分类号： H01L29/155 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7831

摘要： Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.

摘要翻译： 本文通常描述用于提供包括调制掺杂晶体管的三维互补金属氧化物半导体器件的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US20130341704A1

公开(公告)日：2013-12-26

申请号：US13997162

申请日：2011-12-30

申请人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Seung Hoon Sung

发明人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Seung Hoon Sung

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02603 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858 ,  Y10S977/762 ,  Y10S977/89 ,  Y10S977/938

摘要： Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.

摘要翻译： 本文描述了具有一个或多个活性纳米线和一个或多个非活性纳米线的基于纳米线的栅极全周极晶体管器件。 还描述了制造这种装置的方法。 本发明的一个或多个实施例涉及用于改变包括具有不同数量的纳米线的纳米线堆叠的晶体管结构的栅极宽度的方法。 这些方法包括使一定数量的纳米线无效（即使得电流不流过纳米线），通过切断沟道区，掩埋源区和漏区，或两者。 总之，具有多个纳米线的纳米线基结构的栅极宽度可以通过使一定数量的纳米线无效而保持其它纳米线作为活性而变化。

公开(公告)号：US20130334499A1

公开(公告)日：2013-12-19

申请号：US13957965

申请日：2013-08-02

申请人： Benjamin Chu-Kung ,  Uday Shah ,  Ravi Pillarisetty ,  Been-Yin Jin ,  Marko Radosavljevic ,  Willy Rachmady

发明人： Benjamin Chu-Kung ,  Uday Shah ,  Ravi Pillarisetty ,  Been-Yin Jin ,  Marko Radosavljevic ,  Willy Rachmady

IPC分类号： H01L29/06 ,  H01L29/775 ,  H01L21/762

CPC分类号： H01L29/06 ,  B82Y99/00 ,  H01L21/76205 ,  H01L21/76224 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7854

摘要： A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.

摘要翻译： 提供了一种方法。 该方法包括在衬底的顶表面上形成多个纳米线并形成与多个纳米线中的每一个的底表面相邻的氧化物层，其中氧化物层将多个纳米线与衬底隔离。

公开(公告)号：US08575653B2

公开(公告)日：2013-11-05

申请号：US12924307

申请日：2010-09-24

申请人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Robert Chau

发明人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Robert Chau

IPC分类号： H01L29/66

CPC分类号： H01L29/7851 ,  B82Y10/00 ,  H01L21/30604 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/151 ,  H01L29/165 ,  H01L29/267 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

摘要： Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

公开(公告)号：US20130062594A1

公开(公告)日：2013-03-14

申请号：US13291682

申请日：2011-11-08

申请人： Benjamin Chu-Kung ,  Uday Shah ,  Ravi Pillarisetty ,  Been-Yih Jin ,  Marko Radosavljevic ,  Willy Rachmady

发明人： Benjamin Chu-Kung ,  Uday Shah ,  Ravi Pillarisetty ,  Been-Yih Jin ,  Marko Radosavljevic ,  Willy Rachmady

IPC分类号： H01L29/06 ,  H01L29/775

CPC分类号： H01L29/06 ,  B82Y99/00 ,  H01L21/76205 ,  H01L21/76224 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7854

摘要： A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.

公开(公告)号：US08344418B2

公开(公告)日：2013-01-01

申请号：US12646436

申请日：2009-12-23

申请人： Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Robert S. Chau

发明人： Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Robert S. Chau

IPC分类号： H01L31/102

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/78

摘要： A group III chalcogenide layer for interfacing a high-k dielectric to a III-V semiconductor surface and methods of forming the same. A III-V QWFET includes a gate stack which comprises a high-K gate dielectric layer disposed on an interfacial layer comprising a group III chalcogenide. In an embodiment, a III-V semiconductor surface comprising a native oxide is sequentially exposed to TMA and H2S provided in an ALD process to remove substantially all the native oxide and form an Al2S3 layer on the semiconductor surface.

摘要翻译： 用于将高k电介质与III-V半导体表面接合的III族硫属化物层及其形成方法。 III-V QWFET包括栅极堆叠，其包括设置在包含III族硫族化物的界面层上的高K栅极电介质层。 在一个实施方案中，包含天然氧化物的III-V半导体表面依次暴露于在ALD工艺中提供的TMA和H 2 S以去除基本上所有的天然氧化物并在半导体表面上形成Al 2 S 3层。

公开(公告)号：US08283653B2

公开(公告)日：2012-10-09

申请号：US12646477

申请日：2009-12-23

申请人： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been Y. Jin ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been Y. Jin ,  Robert S. Chau

IPC分类号： H01L29/06

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7782 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

摘要翻译： 公开了用于形成非平面锗量子阱结构的技术。 特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。 在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。 在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。

公开(公告)号：US08264048B2

公开(公告)日：2012-09-11

申请号：US12032603

申请日：2008-02-15

申请人： Willy Rachmady ,  Uday Shah ,  Jack T. Kavalieros

发明人： Willy Rachmady ,  Uday Shah ,  Jack T. Kavalieros

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/42376 ,  H01L21/28114 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A multi-gate device having a T-shaped gate structure is generally described. In one example, an apparatus includes a semiconductor substrate, at least one multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a gate region, a source region, and a drain region, the gate region being positioned between the source and drain regions, a gate dielectric coupled to the gate region of the multi-gate fin, a gate electrode coupled to the gate dielectric, the gate electrode having a first thickness and a second thickness, the second thickness being greater than the first thickness, a first spacer dielectric coupled to a portion of the gate electrode having the first thickness, and a second spacer dielectric coupled to the first spacer dielectric and coupled to the gate electrode where the second spacer dielectric is coupled to a portion of the gate electrode having the second thickness.

摘要翻译： 通常描述具有T形栅极结构的多栅极器件。 在一个示例中，设备包括半导体衬底，与半导体衬底耦合的至少一个多栅极鳍，多栅极鳍具有栅极区，源极区和漏极区，栅极区位于 源极和漏极区域，耦合到多栅极鳍的栅极区域的栅极电介质，耦合到栅极电介质的栅电极，栅电极具有第一厚度和第二厚度，第二厚度大于第一厚度 耦合到具有第一厚度的栅电极的一部分的第一间隔电介质和耦合到第一间隔电介质并耦合到栅电极的第二间隔电介质，其中第二间隔电介质耦合到栅电极的一部分， 第二厚度。

公开(公告)号：US08193641B2

公开(公告)日：2012-06-05

申请号：US11431388

申请日：2006-05-09

申请人： Willy Rachmady ,  Brian McIntyre ,  Michael K. Harper ,  Subhash M. Joshi

发明人： Willy Rachmady ,  Brian McIntyre ,  Michael K. Harper ,  Subhash M. Joshi

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/66553

摘要： A transistor gate comprises a substrate having a pair of spacers disposed on a surface, a high-k dielectric conformally deposited on the substrate between the spacers, a recessed workfunction metal conformally deposited on the high-k dielectric and along a portion of the spacer sidewalls, a second workfunction metal conformally deposited on the recessed workfunction metal, and an electrode metal deposited on the second workfunction metal. The transistor gate may be formed by conformally depositing the high-k dielectric into a trench between the spacers on the substrate, conformally depositing a workfunction metal atop the high-k dielectric, depositing a sacrificial mask atop the workfunction metal, etching a portion of the sacrificial mask to expose a portion of the workfunction metal, and etching the exposed portion of the workfunction metal to form the recessed workfunction metal. The second workfunction metal and the electrode metal may be deposited atop the recessed workfunction metal.

摘要翻译： 晶体管栅极包括具有设置在表面上的一对间隔物的衬底，在隔离体之间保形地沉积在衬底上的高k电介质，共形沉积在高k电介质上并沿着间隔壁侧壁的一部分的凹陷功函数金属 保形地沉积在凹陷功函数金属上的第二功函件金属和沉积在第二功函数金属上的电极金属。 晶体管栅极可以通过将高k电介质保形地沉积到衬底上的间隔物之间​​的沟槽中而形成，从而在高k电介质顶部上共形沉积功函数金属，在功函数金属顶部沉积牺牲掩模，蚀刻部分 牺牲掩模以暴露所述功函数金属的一部分，以及蚀刻所述功函数金属的暴露部分以形成所述凹陷功函数金属。 第二功函数金属和电极金属可沉积在凹陷功函数金属顶上。

公开(公告)号：US08106440B2

公开(公告)日：2012-01-31

申请号：US12632753

申请日：2009-12-07

申请人： Willy Rachmady ,  Marko Radosavljevic ,  Mantu K. Hudait ,  Matthew V Metz

发明人： Willy Rachmady ,  Marko Radosavljevic ,  Mantu K. Hudait ,  Matthew V Metz

IPC分类号： H01L29/94

CPC分类号： H01L21/0228 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/28273 ,  H01L21/312 ,  H01L21/3141 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/517 ,  H01L29/78

摘要： Embodiments of the present invention describe a method of fabricating a III-V quantum well transistor with low current leakage and high on-to-off current ratio. A hydrophobic mask having an opening is formed on a semiconductor film. The opening exposes a portion on the semiconductor film where a dielectric layer is desired to be formed. A hydrophilic surface is formed on the exposed portion of the semiconductor film. A dielectric layer is then formed on the hydrophilic surface by using an atomic layer deposition process. A metal layer is deposited on the dielectric layer.

摘要翻译： 本发明的实施例描述了一种制造具有低电流泄漏和高导通截止电流比的III-V量子阱晶体管的方法。 在半导体膜上形成具有开口的疏水性掩模。 该开口暴露出希望形成介电层的半导体膜上的一部分。 亲水表面形成在半导体膜的暴露部分上。 然后通过使用原子层沉积工艺在亲水表面上形成介电层。 金属层沉积在电介质层上。