公开(公告)号：US20190043569A1

公开(公告)日：2019-02-07

申请号：US16048364

申请日：2018-07-30

Applicant: Winbond Electronics Corp.

Inventor： Chiang-Hung Chen ,  Yao-Ting Tsai ,  Wen Hung ,  Yu-Kai Liao

IPC: G11C11/56 ,  H01L23/528 ,  H01L23/532 ,  H01L29/51 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11582 ,  G11C16/04 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/3215

Abstract: Provided is a three dimensional memory including a substrate, a plurality of source lines, a plurality of isolation structures, a plurality of drain lines, a plurality of bit lines, a plurality of charge storage structures, and a plurality of conductive layers. The source lines are located on the substrate. The isolation structures are respectively located between the source lines, so as to electrically isolate the source lines from each other. The drain lines are located on the source lines. Extending directions of the source lines and the drain lines are different. The bit lines extend from the source lines to the drain lines. The charge storage structures respectively surround the bit lines. The conductive layer respectively cover surfaces of the charge storage structures arranged along each of the source lines.

公开(公告)号：US20180204846A1

公开(公告)日：2018-07-19

申请号：US15922888

申请日：2018-03-15

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Hsiu-Han Liao ,  Yao-Ting Tsai

IPC: H01L27/11521 ,  H01L29/417

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/41758 ,  H01L29/42328 ,  H01L29/4975 ,  H01L29/66825 ,  H01L29/7883

Abstract: Provided is a memory device including a substrate, a source region, a drain region, a source contact, a drain contact, at least two stack gates, and at least two selection gates. The source region and the drain region are both located in the substrate. The source contact is located on the source region and the drain contact is located on the drain region. A bottom area of the drain contact is greater than a bottom area of the source contact. The stack gates are located on the substrate at two sides of the source region respectively. The selection gates are located on the substrate at two sides of the drain region respectively. A distance between the selection gates located at two sides of the drain region is greater than a distance between the stack gates located at two sides of the source region.

公开(公告)号：US20180047737A1

公开(公告)日：2018-02-15

申请号：US15352594

申请日：2016-11-16

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Hsiu-Han Liao ,  Yao-Ting Tsai

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L21/28 ,  H01L29/788 ,  H01L29/49

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/41758 ,  H01L29/42328 ,  H01L29/4975 ,  H01L29/66825 ,  H01L29/7883

Abstract: Provided is a memory device including a substrate and a gate structure. The gate structure is located on the substrate. The gate structure includes a stack gate and a selection gate aside the stack structure. A topmost surface of the selection gate is lower than a topmost surface of the stack gate.

公开(公告)号：US11974428B2

公开(公告)日：2024-04-30

申请号：US17564259

申请日：2021-12-29

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC: H10B41/30 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/66825 ,  H01L29/7883

Abstract: Provided are a memory device and a method of manufacturing the same. The memory device includes: a stack structure; a first source/drain region and a second source/drain region located in a substrate beside the stack structure; a first self-aligned contact connected to the first source/drain region; a second self-aligned contact connected to the second source/drain region; a first liner structure located between the first self-aligned contact and a first sidewall of the stack structure; and a second liner structure located between the second self-aligned contact and a second sidewall of the stack structure. The first liner structure and the second liner structure are not connected and do not cover the stack structure.

公开(公告)号：US20240021266A1

公开(公告)日：2024-01-18

申请号：US17866558

申请日：2022-07-18

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Che-Fu Chuang

IPC: G11C29/00 ,  G11C29/52

CPC classification number: G11C29/72 ,  G11C29/785 ,  G11C29/52

Abstract: A memory array is provided. The memory array includes multiple memory blocks, each including multiple data storage regions and multiple groups of word lines. Each group of word lines extend across one of the memory blocks. The groups of word lines are connected to multiple overlying signal lines through multiple groups of first word line contact regions in the memory blocks and multiple second word line contact regions between the memory blocks.

公开(公告)号：US11818884B2

公开(公告)日：2023-11-14

申请号：US17545519

申请日：2021-12-08

Applicant: Winbond Electronics Corp.

Inventor： Chien-Hsien Wu ,  Chun-Hung Lin ,  Kao-Tsair Tsai ,  Yao-Ting Tsai

IPC: H01L21/3105 ,  H01L21/76 ,  H10B41/00 ,  H01L29/66

CPC classification number: H10B41/00 ,  H01L29/66825

Abstract: A method for manufacturing a non-volatile memory device is provided. The method includes forming a trench through a sacrificial layer and extending into a substrate, filling a first insulating material into the trench, and implanting a dopant in the first insulating material by an implantation process. Then, the first insulating material is partially removed to form a first recess between the sacrificial layers. The lowest point of the first recess is lower than the top surface of the substrate. The method includes filling a second insulating material in the first recess and removing the sacrificial layer to form a second recess adjacent to the second insulating material. The method includes forming a first polycrystalline silicon layer in the second recess, and sequentially forming a dielectric layer and a second polycrystalline silicon layer on the first polycrystalline silicon layer.

公开(公告)号：US11805644B2

公开(公告)日：2023-10-31

申请号：US17567850

申请日：2022-01-03

Applicant: Winbond Electronics Corp.

Inventor： Jian-Ting Chen ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC: H01L27/11556 ,  H10B41/27 ,  H01L29/788 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H10B41/27 ,  H01L21/823437 ,  H01L29/66825 ,  H01L29/788

Abstract: Provided is a manufacturing method of a memory device, including: forming a stacked layer on a substrate; patterning the stacked layer to form a plurality of openings in the stacked layer; forming a spacer on a sidewall of the openings; performing a first etching process by using the spacer as a mask to form a plurality of stack structures, wherein the spacer is embedded in the stack structures, such that a width of an upper portion of the stack structures is less than a width of a lower portion thereof; forming a dielectric layer on the stack structures and the spacer; and respectively forming a plurality of contact plugs on the substrate between the stack structures.

公开(公告)号：US20230017264A1

公开(公告)日：2023-01-19

申请号：US17375000

申请日：2021-07-14

Applicant: Winbond Electronics Corp.

Inventor： Yu-Lung Wang ,  Yao-Ting Tsai ,  Jian-Ting Chen ,  Yuan-Huang Wei

IPC: H01L29/788 ,  H01L27/11521 ,  H01L29/417 ,  H01L21/311 ,  H01L29/66 ,  H01L29/40

Abstract: Provided is a semiconductor device including a substrate, multiple first gate structures, and a protective structure. The substrate includes a first region and a second region. The first gate structures are disposed on the substrate in the first region. The protective structure conformally covers a sidewall of one of the first gate structures adjacent to the second region. The protective structure includes a lower portion and an upper portion disposed on the lower portion. The lower portion and the upper portion have different dielectric materials. A method of forming a semiconductor device is also provided.

公开(公告)号：US11251273B2

公开(公告)日：2022-02-15

申请号：US16521311

申请日：2019-07-24

Applicant: Winbond Electronics Corp.

Inventor： Jian-Ting Chen ,  Yao-Ting Tsai ,  Jung-Ho Chang ,  Hsiu-Han Liao

IPC: H01L21/28 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3215 ,  H01L21/311 ,  H01L29/788 ,  H01L29/49

Abstract: A non-volatile memory device and its manufacturing method are provided. The method includes the following steps. A plurality of isolation structures are formed in a substrate. A first polycrystalline silicon layer is formed in the substrate and between two adjacent isolation structures. A first implantation process is performed to implant a first dopant into the first polycrystalline silicon layer and the isolation structures. A portion of each of the isolation structures is partially removed, and the remaining portion of each of the isolation structures has a substantially flat top surface. An annealing process is performed after partially removing the isolation structures to uniformly diffuse the first dopant in the first polycrystalline silicon layer. A dielectric layer is formed on the first polycrystalline silicon layer, and a second polycrystalline silicon layer is formed on the dielectric layer.

公开(公告)号：US20210183874A1

公开(公告)日：2021-06-17

申请号：US16713020

申请日：2019-12-13

Applicant: Winbond Electronics Corp.

Inventor： Hsin-Huang Shen ,  Yu-Shu Cheng ,  Yao-Ting Tsai

IPC: H01L27/11521 ,  H01L27/11531 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L21/762 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a plurality of floating gates, a tunneling dielectric layer, a plurality of control gates, and an ONO layer. The floating gates are located on the substrate, and the tunneling dielectric layer is located between the substrate and each of the floating gates. The control gates are located on the floating gates, and the ONO layer is located on two sidewalls of each of the control gates and between each of the control gates and each of the floating gates.