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    Apparatus and methods for encapsulating microelectromechanical (MEM) devices on a wafer scale
    16.
    发明申请
    Apparatus and methods for encapsulating microelectromechanical (MEM) devices on a wafer scale 有权
    用于将微机电（MEM）器件封装在晶片上的装置和方法

    公开(公告)号：US20060108675A1

    公开(公告)日：2006-05-25

    申请号：US10993548

    申请日：2004-11-19

    申请人： Evan Colgan ,  Bruce Furman ,  Christopher Jahnes

    发明人： Evan Colgan ,  Bruce Furman ,  Christopher Jahnes

    IPC分类号： H01L21/50 ,  H01L23/06 ,  H01L21/48 ,  H01L21/44

    CPC分类号： B81C1/00293 ,  B81C2203/0145

    摘要： Apparatus and methods are provided for enabling wafer-scale encapsulation of microelectromechanical (MEM) devices (e.g., resonators, filters) to protect the MEMs from the ambient and to provide either a controlled ambient or a reduced pressure. In particular, methods for wafer-scale encapsulation of MEM devices are provided, which enable encapsulation of MEM devices under desired ambient conditions that are not determined by the deposition conditions of a sealing process in which MEM release via holes are sealed or pinched-off, and which prevent sealing material from being inadvertently deposited on the MEM device during the sealing process.

    摘要翻译： 提供了设备和方法，用于实现微机电（MEM）装置（例如，谐振器，滤波器）的晶片级封装，以保护MEM免受环境影响，并提供受控的环境或减压。 特别地，提供了用于MEM器件的晶片级封装的方法，其能够在期望的环境条件下封装MEM器件，所述环境条件不是通过其中MEM释放通孔被密封或夹断的密封过程的沉积条件来确定的， 并且其在密封过程中防止密封材料被无意中沉积在MEM装置上。

    Process for fabricating copper interconnects in ultra large scale integrated (ULSI) circuits
    18.
    发明授权
    Process for fabricating copper interconnects in ultra large scale integrated (ULSI) circuits 失效
    在超大规模集成（ULSI）电路中制造铜互连的工艺

    公开(公告)号：US5277985A

    公开(公告)日：1994-01-11

    申请号：US790971

    申请日：1991-11-12

    申请人： Jian Li ,  Evan Colgan ,  James W. Mayer

    发明人： Jian Li ,  Evan Colgan ,  James W. Mayer

    IPC分类号： H01L21/768 ,  H01L23/532 ,  B32B9/00

    CPC分类号： H01L21/76867 ,  H01L21/76838 ,  H01L21/76852 ,  H01L21/76886 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T428/24917

    摘要： The present invention features low-temperature, self-encapsulated, copper interconnect lines on silicon substrates of Ultra-Large Scale Integration (ULSI) circuits. The interconnect lines are a product of a process that includes the following steps: (a) alloying the copper with titanium in an approximate 10 atomic weight percentage of titanium; (b) depositing a layer of the copper/titanium alloy upon a silicon dioxide/silicon substrate of a ULSI circuit; (c) patterning the copper/titanium layer to form interconnect lines on the substrate; (d) forming a titanium rich surface film on the copper interconnect lines by rapid heating of the copper/titanium interconnect lines at an approximate ramping rate of between 60.degree. and 80.degree. C./minute; and (e) nitriding the titanium rich surface of the interconnect lines in an ammonia atmosphere at low temperatures in an approximate range of between 450.degree. to 650.degree. C. for about 15 to 40 minutes, to form a titanium nitride encapsulating layer about said copper interconnect lines.

    摘要翻译： 本发明在超大规模集成（ULSI）电路的硅衬底上具有低温，自封装的铜互连线。 互连线是包括以下步骤的工艺的产物：（a）将铜与约10原子量的钛的钛合金化; （b）将铜/钛合金层沉积在ULSI电路的二氧化硅/硅衬底上; （c）图案化铜/钛层以在衬底上形成互连线; （d）通过铜/钛互连线以60摄氏度到80摄氏度/分钟的近似斜率的快速加热在铜互连线上形成富钛表面膜; 并且（e）在氨气气氛中在约450至650℃的近似范围内的低温下将互连线的富钛表面渗氮约15至40分钟，以形成围绕所述铜的氮化钛封装层 互连线。