公开(公告)号：US20090050974A1

公开(公告)日：2009-02-26

申请号：US12244573

申请日：2008-10-02

申请人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

发明人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

IPC分类号： H01L47/00 ,  H01L21/8234

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

摘要翻译： 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

公开(公告)号：US20080128688A1

公开(公告)日：2008-06-05

申请号：US12016701

申请日：2008-01-18

申请人： Yaoling Pan ,  Francisco Leon ,  David P. Stumbo

发明人： Yaoling Pan ,  Francisco Leon ,  David P. Stumbo

IPC分类号： H01L51/05

CPC分类号： H01L51/0545 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/0048 ,  H01L51/0049 ,  H01L51/0541 ,  H01L51/0566 ,  H01L51/4253 ,  H01L51/4266 ,  Y02E10/549 ,  Y02P70/521 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764

摘要： The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.

摘要翻译： 本发明涉及使用并入和/或设置在导电聚合物层附近的纳米线（或诸如纳米带，纳米管等的其它纳米结构）的薄膜晶体管，以及用于生产这种晶体管的生产可扩展方法。 特别地，公开了包含导电聚合材料如聚苯胺（PANI）或聚吡咯（PPY）和一个或多个纳米线的复合材料，其中并入其中。 还提供了几种纳米线TFT制造方法，其在一个示例性实施例中包括提供器件衬底; 在器件衬底上沉积第一导电聚合物材料层; 限定所述导电聚合物层中的一个或多个栅极接触区域; 在所述导电聚合物层上以足够的纳米线密度沉积多个纳米线以实现工作电流水平; 在所述多个纳米线上沉积第二导电聚合物材料层; 以及在所述第二导电聚合物材料层中形成源极和漏极接触区域，从而提供与所述多个纳米线的电连接性，由此所述纳米线形成在所述源极和漏极区域中的相应长度之间具有长度的沟道。

公开(公告)号：US07339184B2

公开(公告)日：2008-03-04

申请号：US11117707

申请日：2005-04-29

申请人： Linda T. Romano ,  Jian Chen ,  Xiangfeng Duan ,  Robert S. Dubrow ,  Stephen A. Empedocles ,  Jay L. Goldman ,  James M. Hamilton ,  David L. Heald ,  Francesco Lemmi ,  Chunming Niu ,  Yaoling Pan ,  George Pontis ,  Vijendra Sahi ,  Erik C. Scher ,  David P. Stumbo ,  Jeffery A. Whiteford

发明人： Linda T. Romano ,  Jian Chen ,  Xiangfeng Duan ,  Robert S. Dubrow ,  Stephen A. Empedocles ,  Jay L. Goldman ,  James M. Hamilton ,  David L. Heald ,  Francesco Lemmi ,  Chunming Niu ,  Yaoling Pan ,  George Pontis ,  Vijendra Sahi ,  Erik C. Scher ,  David P. Stumbo ,  Jeffery A. Whiteford

IPC分类号： H01L29/00

CPC分类号： C30B29/605 ,  B82Y10/00 ,  C30B11/12 ,  H01L21/02439 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/02653 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0048 ,  Y10S977/762 ,  Y10S977/938 ,  Y10T428/139 ,  Y10T428/2902 ,  Y10T428/2949

摘要： The present invention is directed to methods to harvest, integrate and exploit nanomaterials, and particularly elongated nanowire materials. The invention provides methods for harvesting nanowires that include selectively etching a sacrificial layer placed on a nanowire growth substrate to remove nanowires. The invention also provides methods for integrating nanowires into electronic devices that include placing an outer surface of a cylinder in contact with a fluid suspension of nanowires and rolling the nanowire coated cylinder to deposit nanowires onto a surface. Methods are also provided to deposit nanowires using an ink-jet printer or an aperture to align nanowires. Additional aspects of the invention provide methods for preventing gate shorts in nanowire based transistors. Additional methods for harvesting and integrating nanowires are provided.

摘要翻译： 本发明涉及收获，整合和利用纳米材料，特别是细长的纳米线材料的方法。 本发明提供了收获纳米线的方法，其包括选择性地蚀刻放置在纳米线生长衬底上以去除纳米线的牺牲层。 本发明还提供了将纳米线整合到电子器件中的方法，包括将圆筒的外表面与纳米线的流体悬浮液接触并滚动纳米线涂覆的圆筒以将纳米线沉积到表面上。 还提供了使用喷墨打印机或孔径以纳米线排列纳米线的方法。 本发明的另外的方面提供了用于防止基于纳米线的晶体管中的栅极短路的方法。 提供了收获和集成纳米线的其他方法。

公开(公告)号：US20050212079A1

公开(公告)日：2005-09-29

申请号：US10806361

申请日：2004-03-23

申请人： David Stumbo ,  Jian Chen ,  David Heald ,  Yaoling Pan

发明人： David Stumbo ,  Jian Chen ,  David Heald ,  Yaoling Pan

IPC分类号： H01L29/06 ,  H01L29/93

CPC分类号： B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/93 ,  Y10S977/762

摘要： A nanowire varactor diode and methods of making the same are disclosed. The structure comprises a coaxial capacitor running the length of the semiconductor nanowire. In one embodiment, a semiconductor nanowire of a first conductivity type is deposited on a substrate. An insulator is formed on at least a portion of the nanowire's surface. A region of the nanowire is doped with a second conductivity type material. A first electrical contact is formed on at least part of the insulator and the doped region. A second electrical contact is formed on a non-doped potion of the nanowire. During operation, the conductivity type at the surface of the nanowire inverts and a depletion region is formed upon application of a voltage to the first and second electrical contacts. The varactor diode thereby exhibits variable capacitance as a function of the applied voltage.

摘要翻译： 公开了一种纳米线变容二极管及其制造方法。 该结构包括运行半导体纳米线长度的同轴电容器。 在一个实施例中，第一导电类型的半导体纳米线沉积在衬底上。 在纳米线表面的至少一部分上形成绝缘体。 纳米线的区域掺杂有第二导电类型的材料。 在绝缘体和掺杂区域的至少一部分上形成第一电接触。 在纳米线的非掺杂药液上形成第二电接触。 在操作期间，纳米线表面的导电类型反转，并且在向第一和第二电触点施加电压时形成耗尽区。 因此，变容二极管作为施加电压的函数呈现可变电容。

公开(公告)号：US20050064185A1

公开(公告)日：2005-03-24

申请号：US10910800

申请日：2004-08-04

申请人： Mihai Buretea ,  Jian Chen ,  Calvin Chow ,  Chunming Niu ,  Yaoling Pan ,  J. Parce ,  Linda Romano ,  David Stumbo

发明人： Mihai Buretea ,  Jian Chen ,  Calvin Chow ,  Chunming Niu ,  Yaoling Pan ,  J. Parce ,  Linda Romano ,  David Stumbo

IPC分类号： D02G3/00 ,  H01L21/336 ,  H01L21/44 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L33/06 ,  H01L33/24 ,  H01L51/00 ,  H01L51/05

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78681 ,  H01L29/78696 ,  H01L33/06 ,  H01L33/24 ,  H01L51/0048 ,  H01L51/0545 ,  H01L2924/0002 ,  Y10T428/2913 ,  H01L2924/00

摘要： The present invention relates to a system and process for producing a nanowire-material composite. A substrate having nanowires attached to a portion of at least one surface is provided. A material is deposited over the portion to form the nanowire-material composite. The process further optionally comprises separating the nanowire-material composite from the substrate to form a freestanding nanowire-material composite. The freestanding nanowire material composite is optionally further processed into a electronic substrate. A variety of electronic substrates can be produced using the methods described herein. For example, a multi-color light-emitting diode can be produced from multiple, stacked layers of nanowire-material composites, each composite layer emitting light at a different wavelength.

摘要翻译： 本发明涉及纳米线材料复合体的制造方法和制造方法。 提供了具有连接到至少一个表面的一部分的纳米线的衬底。 在该部分上沉积材料以形成纳米线材料复合材料。 该方法进一步任选地包括从衬底分离纳米线材料复合物以形成独立的纳米线材料复合材料。 独立的纳米线材料复合材料任选进一步加工成电子基片。 可以使用本文所述的方法来生产各种电子基板。 例如，多个发光二极管可以由多个层叠的纳米线材料复合体制成，每个复合层发射不同波长的光。

公开(公告)号：US08817358B2

公开(公告)日：2014-08-26

申请号：US13565688

申请日：2012-08-02

申请人： John Hyunchul Hong ,  Isak Clark Reines ,  Chong Uk Lee ,  Tallis Young Chang ,  Yaoling Pan ,  Edward Keat Leem Chan

发明人： John Hyunchul Hong ,  Isak Clark Reines ,  Chong Uk Lee ,  Tallis Young Chang ,  Yaoling Pan ,  Edward Keat Leem Chan

IPC分类号： G02B26/00 ,  G02F1/03

CPC分类号： G02B26/001

摘要： This disclosure provides systems, methods and apparatus for a thin film stack with surface-conditioning buffer layers. In one aspect, the thin film stack includes a plurality of thin film layers each having a thickness greater than about 10 nm and a plurality of surface-conditioning buffer layers each having a thickness between about 1 nm and about 10 nm. The surface-conditioning buffer layers are alternatingly disposed between the thin film layers. Each of the surface-conditioning buffer layers are formed with the same or substantially the same thickness and composition. In some implementations, the surface-conditioning buffer layers are formed by atomic layer deposition.

摘要翻译： 本公开提供了具有表面调节缓冲层的薄膜堆叠的系统，方法和装置。 在一个方面，薄膜堆叠包括多个厚度大于约10nm的薄膜层以及各自具有约1nm至约10nm厚度的多个表面调节缓冲层。 表面调节缓冲层交替地设置在薄膜层之间。 每个表面调节缓冲层以相同或基本上相同的厚度和组成形成。 在一些实施方案中，表面调节缓冲层通过原子层沉积形成。

公开(公告)号：US08797303B2

公开(公告)日：2014-08-05

申请号：US13052446

申请日：2011-03-21

申请人： Cheonhong Kim ,  John Hyunchul Hong ,  Yaoling Pan

发明人： Cheonhong Kim ,  John Hyunchul Hong ,  Yaoling Pan

IPC分类号： G09G5/00 ,  H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  G02B26/00

CPC分类号： H01L29/66742 ,  G02B26/001 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78693

摘要： This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source region, a drain region, and a channel region between the source region and the drain region is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel region, and a first metal layer on the dielectric layer. A second metal layer is formed on the oxide semiconductor layer overlying the source region and the drain region. The oxide semiconductor layer and the second metal layer are treated to form a heavily doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source region and the drain region. An oxide in the second metal layer also can be formed.

摘要翻译： 本公开提供了用于制造薄膜晶体管器件的系统，方法和装置。 一方面，提供了在源极区域和漏极区域之间具有源极区域，漏极区域和沟道区域的衬底。 衬底还包括氧化物半导体层，覆盖沟道区的第一介电层和介电层上的第一金属层。 在覆盖源极区域和漏极区域的氧化物半导体层上形成第二金属层。 处理氧化物半导体层和第二金属层以在覆盖源极区和漏极区的氧化物半导体层中形成重掺杂的n型氧化物半导体。 也可以形成第二金属层中的氧化物。

公开(公告)号：US20100167512A1

公开(公告)日：2010-07-01

申请号：US12720125

申请日：2010-03-09

申请人： Yaoling Pan ,  Jian Chen ,  Francisco Leon ,  Shahriar Mostarshed ,  Linda T. Romano ,  Vijendra Sahi ,  David P. Stumbo

发明人： Yaoling Pan ,  Jian Chen ,  Francisco Leon ,  Shahriar Mostarshed ,  Linda T. Romano ,  Vijendra Sahi ,  David P. Stumbo

IPC分类号： H01L21/22

CPC分类号： H01L29/0665 ,  B81C1/00698 ,  B81C2201/0173 ,  B82Y10/00 ,  H01L21/2256 ,  H01L21/268 ,  H01L29/0673

摘要： Methods of doping nanostructures, such as nanowires, are disclosed. The methods provide a variety of approaches for improving existing methods of doping nanostructures. The embodiments include the use of a sacrificial layer to promote uniform dopant distribution within a nanostructure during post-nanostructure synthesis doping. In another embodiment, a high temperature environment is used to anneal nanostructure damage when high energy ion implantation is used. In another embodiment rapid thermal annealing is used to drive dopants from a dopant layer on a nanostructure into the nanostructure. In another embodiment a method for doping nanowires on a plastic substrate is provided that includes depositing a dielectric stack on a plastic substrate to protect the plastic substrate from damage during the doping process. An embodiment is also provided that includes selectively using high concentrations of dopant materials at various times in synthesizing nanostructures to realize novel crystallographic structures within the resulting nanostructure.

摘要翻译： 公开了掺杂纳米结构的方法，例如纳米线。 该方法提供了改进现有掺杂纳米结构方法的各种方法。 这些实施方案包括在后纳米结构合成掺杂期间使用牺牲层来促进纳米结构内的均匀掺杂剂分布。 在另一个实施例中，当使用高能离子注入时，使用高温环境退火纳米结构损伤。 在另一个实施方案中，使用快速热退火来将掺杂剂从纳米结构上的掺杂剂层驱动到纳米结构中。 在另一个实施例中，提供了一种在塑料衬底上掺杂纳米线的方法，其包括在塑料衬底上沉积电介质叠层以保护塑料衬底免于在掺杂过程期间损坏。 还提供了一种实施方案，其包括在合成纳米结构中在不同时间选择性地使用高浓度的掺杂剂材料以在所得纳米结构内实现新的晶体结构。

公开(公告)号：US07701014B2

公开(公告)日：2010-04-20

申请号：US12244573

申请日：2008-10-02

申请人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

发明人： Shahriar Mostarshed ,  Jian Chen ,  Francisco Leon ,  Yaoling Pan ,  Linda T. Romano

IPC分类号： H01L27/088

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

摘要翻译： 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

公开(公告)号：US07345307B2

公开(公告)日：2008-03-18

申请号：US11233503

申请日：2005-09-22

申请人： Yaoling Pan ,  Francisco Leon ,  David P. Stumbo

发明人： Yaoling Pan ,  Francisco Leon ,  David P. Stumbo

IPC分类号： H01L29/10

CPC分类号： H01L51/0545 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/0048 ,  H01L51/0049 ,  H01L51/0541 ,  H01L51/0566 ,  H01L51/4253 ,  H01L51/4266 ,  Y02E10/549 ,  Y02P70/521 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764

摘要： The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.

摘要翻译： 本发明涉及使用并入和/或设置在导电聚合物层附近的纳米线（或诸如纳米带，纳米管等的其它纳米结构）的薄膜晶体管，以及用于生产这种晶体管的生产可扩展方法。 特别地，公开了包含导电聚合材料如聚苯胺（PANI）或聚吡咯（PPY）和一个或多个纳米线的复合材料，其中并入其中。 还提供了几种纳米线TFT制造方法，其在一个示例性实施例中包括提供器件衬底; 在器件衬底上沉积第一导电聚合物材料层; 限定所述导电聚合物层中的一个或多个栅极接触区域; 在所述导电聚合物层上以足够的纳米线密度沉积多个纳米线以实现工作电流水平; 在所述多个纳米线上沉积第二导电聚合物材料层; 以及在所述第二导电聚合物材料层中形成源极和漏极接触区域，从而提供与所述多个纳米线的电连接性，由此所述纳米线形成在所述源极和漏极区域中的相应长度之间具有长度的沟道。