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    Refresh circuit and refresh method in semiconductor memory device
    11.
    发明申请
    Refresh circuit and refresh method in semiconductor memory device 有权
    半导体存储器件中的刷新电路和刷新方法

    公开(公告)号：US20080080285A1

    公开(公告)日：2008-04-03

    申请号：US11730275

    申请日：2007-03-30

    申请人： Jung Sunwoo ,  Yun-Sang Lee ,  Hoe-Ju Chung

    发明人： Jung Sunwoo ,  Yun-Sang Lee ,  Hoe-Ju Chung

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C11/40618

    摘要： A refresh method for a semiconductor memory device having more than one bank group is provided. The refresh method may include applying an all-refresh command to one the bank groups, determining if one of the bank groups includes a bank undergoing a refresh operation when the all-refresh command is received, and performing an all-refresh operation based on the determination.

    摘要翻译： 提供了具有多于一个组组的半导体存储器件的刷新方法。 刷新方法可以包括：将全刷新命令应用于银行组中的一个，当接收到全刷新命令时，确定银行组中的一个是否包括经历刷新操作的存储体，并且基于所述刷新操作执行全刷新操作 决心。

    Method and apparatus for refreshing memory device
    12.
    发明申请
    Method and apparatus for refreshing memory device 审中-公开
    用于刷新存储器件的方法和装置

    公开(公告)号：US20060044912A1

    公开(公告)日：2006-03-02

    申请号：US11129073

    申请日：2005-05-13

    申请人： Byoung-Sul Kim ,  Yun-Sang Lee

    发明人： Byoung-Sul Kim ,  Yun-Sang Lee

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1042 ,  G11C11/406 ,  G11C11/40618

    摘要： For refreshing a memory device, a refresh selection unit is enabled within a selected group of memory cells for refreshing at least one memory cell within the selected group in response to a refresh control signal and a refresh address signal from an external source. In addition, a normal operation circuit performs a normal operation on at least one memory cell of another group of memory cells while the at least one memory cell within the selected group is being refreshed to reduce refresh overhead.

    摘要翻译： 为了刷新存储器件，刷新选择单元在所选择的存储器单元组内启用，用于响应于来自外部源的刷新控制信号和刷新地址信号刷新所选组中的至少一个存储器单元。 此外，正常操作电路对另一组存储器单元的至少一个存储单元执行正常操作，同时刷新所选组内的至少一个存储单元以减少刷新开销。

    Integrated circuit device having an internal state monitoring function
    13.
    发明授权
    Integrated circuit device having an internal state monitoring function 有权
    具有内部状态监视功能的集成电路装置

    公开(公告)号：US06996754B1

    公开(公告)日：2006-02-07

    申请号：US09672223

    申请日：2000-09-27

    申请人： Yun-Sang Lee

    发明人： Yun-Sang Lee

    IPC分类号： G01R31/28

    CPC分类号： G11C29/48 ,  G11C29/1201

    摘要： An integrated circuit device for testing is disclosed. The device includes a plurality of internal circuits for generating a plurality of internal signals, the internal signals used for addressing storage locations and for controlling internal operations, a first selection circuit for receiving the internal circuits in response to selection signals corresponding to test information signals, a second selection circuit for receiving output signals from the first selection circuit and output signals from a sense amplifier, and for opening an alternative one of transfer paths of the internal signals and the output signals in response to the selection signals, and a data output buffer for transferring output signals from the second selection signals to an outside of the device through data input/output pads.

    摘要翻译： 公开了一种用于测试的集成电路装置。 该装置包括用于产生多个内部信号的多个内部电路，用于寻址存储位置和用于控制内部操作的内部信号，用于响应于与测试信息信号对应的选择信号接收内部电路的第一选择电路， 第二选择电路，用于接收来自第一选择电路的输出信号和来自读出放大器的输出信号，以及响应于选择信号打开内部信号和输出信号的传输路径中的另一个传输路径;以及数据输出缓冲器 用于通过数据输入/输出焊盘将输出信号从第二选择信号传送到设备的外部。

    Semiconductor memory device having write column select line or read column select line for shielding signal line
    14.
    发明授权
    Semiconductor memory device having write column select line or read column select line for shielding signal line 失效
    具有用于屏蔽信号线的写列选择线或读列选择线的半导体存储器件

    公开(公告)号：US06775170B2

    公开(公告)日：2004-08-10

    申请号：US10222110

    申请日：2002-08-16

    申请人： Yun-Sang Lee ,  Won-Chang Jung

    发明人： Yun-Sang Lee ,  Won-Chang Jung

    IPC分类号： G11C702

    CPC分类号： G11C7/02 ,  G11C7/1048 ,  G11C2207/002

    摘要： A semiconductor memory device comprises a write column select line or read column select line for shielding a signal line. The semiconductor memory device may include a signal line, a read column select line, and a write column select line. The signal line may transmit an operation signal related to the operation of the semiconductor memory device. The read column select line may transmit a read column select signal, which may control transfer of a data signal of a bit line to a data line. The write column select line may transmit a write column select signal, which may control transfer of the data signal of the data line to the bit line. One of the read column select line and the write column select line to transmit a deactivated column select signal among the read column select signal and the write column select signal, may be maintained at a predetermined logic level and may shield the signal line.

    摘要翻译： 半导体存储器件包括用于屏蔽信号线的写入列选择线或读取列选择线。 半导体存储器件可以包括信号线，读取列选择线和写入列选择线。 信号线可以发送与半导体存储器件的操作相关的操作信号。 读列选择线可以发送读列选择信号，其可以控制位线的数据信号到数据线的传送。 写列选择线可以发送写列选择信号，其可以控制数据线的数据信号到位线的传送。 在读列选择信号和写列选择信号之间读取列选择线和写列选择线之一发送去激活的列选择信号可以保持在预定的逻辑电平并且可以屏蔽信号线。

    Semiconductor memory device and redundancy method of the same
    15.
    发明授权
    Semiconductor memory device and redundancy method of the same 有权
    半导体存储器件和冗余方法相同

    公开(公告)号：US07535780B2

    公开(公告)日：2009-05-19

    申请号：US11723473

    申请日：2007-03-20

    申请人： Yun-Sang Lee

    发明人： Yun-Sang Lee

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1016 ,  G11C29/42 ,  G11C29/44 ,  G11C29/80 ,  G11C2029/0411 ,  G11C2029/1208

    摘要： A semiconductor memory device may include a memory cell array, a redundancy address decoder, a defective address detection unit, and a defective address program unit. The memory cell array includes a plurality of memory cell groups and a predetermined number of redundancy memory cell groups. The redundancy address decoder includes a predetermined number of redundancy decoders for accessing at least one group of the redundancy memory cell groups when a first defective address is identical to an externally applied address. The defective address detection unit performs a write operation and a read operation on the memory cell array during a test operation to detect a defective address, and outputs the detected defective address as the first defective address when the same defective address is detected a predetermined number of times or more. The defective address program unit receives and programs the first defective address output from the defective address detection unit during a program operation.

    摘要翻译： 半导体存储器件可以包括存储单元阵列，冗余地址解码器，缺陷地址检测单元和缺陷地址程序单元。 存储单元阵列包括多个存储单元组和预定数量的冗余存储单元组。 冗余地址解码器包括预定数量的冗余解码器，用于当第一缺陷地址与外部施加的地址相同时，用于访问至少一组冗余存储单元组。 缺陷地址检测单元在测试操作期间对存储单元阵列执行写入操作和读取操作以检测缺陷地址，并且当检测到相同的缺陷地址时，将检测到的缺陷地址作为第一缺陷地址输出到预定数量的 次以上。 缺陷地址程序单元在编程操作期间接收并编程从缺陷地址检测单元输出的第一缺陷地址。

    Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same
    16.
    发明申请
    Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same 有权
    在使用其的半导体存储器件和半导体存储器件中提供电源电压的方法

    公开(公告)号：US20090067217A1

    公开(公告)日：2009-03-12

    申请号：US12071348

    申请日：2008-02-20

    申请人： Jung Sunwoo ,  Yun-Sang Lee

    发明人： Jung Sunwoo ,  Yun-Sang Lee

    IPC分类号： G11C11/24 ,  G11C5/14 ,  G11C8/08

    CPC分类号： G11C5/147 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4074 ,  G11C11/4096

    摘要： In a method for supplying power supply voltages in a semiconductor memory device a first source voltage is applied to a memory cell of a memory cell array as a cell array internal voltage for operating a sense amplifier coupled to the memory cell. A second source voltage is applied as a word line drive voltage of the memory cell array. The second source voltage has a voltage level higher than a voltage level of the first source voltage. The second source voltage is also applied as a drive voltage of an input/output line driver to drive write data into an input/output line in a write operating mode.

    摘要翻译： 在用于在半导体存储器件中提供电源电压的方法中，第一源电压被施加到存储单元阵列的存储单元，作为用于操作耦合到存储单元的读出放大器的单元阵列内部电压。 施加第二源电压作为存储单元阵列的字线驱动电压。 第二源电压具有高于第一源电压的电压电平的电压电平。 第二源电压也作为输入/输出线驱动器的驱动电压施加，以在写操作模式下将写数据驱动到输入/输出线。