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    Semiconductor constructions having antireflective portions
    11.
    发明授权
    Semiconductor constructions having antireflective portions 有权
    具有抗反射部分的半导体结构

    公开(公告)号：US07804115B2

    公开(公告)日：2010-09-28

    申请号：US11482244

    申请日：2006-07-07

    申请人： Richard Holscher ,  Zhiping Yin ,  Tom Glass

    发明人： Richard Holscher ,  Zhiping Yin ,  Tom Glass

    IPC分类号： H01L31/062 ,  C09K19/00

    CPC分类号： H01L21/0276 ,  G03F7/091 ,  H01L21/3086 ,  Y10T428/1086

    摘要： In one aspect, the invention includes a semiconductor processing method. An antireflective material layer is formed over a substrate. At least a portion of the antireflective material layer is annealed at a temperature of greater than about 400° C. A layer of photoresist is formed over the annealed antireflective material layer. The layer of photoresist is patterned. A portion of the antireflective material layer unmasked by the patterned layer of photoresist is removed. In another aspect, the invention includes the following semiconductor processing. An antireflective material layer is formed over a substrate. The antireflective material layer is annealed at a temperature of greater than about 400° C. A layer of photoresist is formed over the annealed antireflective material layer. Portions of the layer of photoresist are exposed to radiation waves. Some of the radiation waves are absorbed by the antireflective material during the exposing.

    摘要翻译： 一方面，本发明包括半导体处理方法。 在基板上形成防反射材料层。 抗反射材料层的至少一部分在大于约400℃的温度下退火。在退火的抗反射材料层上形成一层光致抗蚀剂。 图案化光刻胶层。 除去由图案化的光致抗蚀剂层掩蔽的抗反射材料层的一部分。 另一方面，本发明包括以下半导体处理。 在基板上形成防反射材料层。 抗反射材料层在大于约400℃的温度下退火。在退火的抗反射材料层上形成一层光致抗蚀剂。 光致抗蚀剂层的一部分暴露于辐射波。 一些辐射波在曝光期间被抗反射材料吸收。

    Interconnect structures with interlayer dielectric
    12.
    发明授权
    Interconnect structures with interlayer dielectric 失效
    互连结构与层间电介质

    公开(公告)号：US07659630B2

    公开(公告)日：2010-02-09

    申请号：US11841180

    申请日：2007-08-20

    申请人： Zhiping Yin ,  Mark E. Jost

    发明人： Zhiping Yin ,  Mark E. Jost

    IPC分类号： H01L21/31

    CPC分类号： H01L21/76849 ,  H01L21/76801 ,  H01L21/76867

    摘要： The present invention relates to metallic interconnect having an interlayer dielectric thereover, the metallic interconnect having an upper surface substantially free from oxidation. The metallic interconnect may have an exposed upper surface thereon that is passivated by a nitrogen containing compound.

    摘要翻译： 本发明涉及在其上具有层间电介质的金属互连，金属互连具有基本上没有氧化的上表面。 金属互连可以在其上具有被含氮化合物钝化的暴露的上表面。

    Fabrication of semiconductor devices using anti-reflective coatings
    14.
    发明授权
    Fabrication of semiconductor devices using anti-reflective coatings 有权
    使用抗反射涂层制造半导体器件

    公开(公告)号：US07589015B2

    公开(公告)日：2009-09-15

    申请号：US11698072

    申请日：2007-01-26

    申请人： Gurtej S. Sandhu ,  Zhiping Yin

    发明人： Gurtej S. Sandhu ,  Zhiping Yin

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/0276 ,  G03F7/091 ,  H01L21/0275 ,  H01L21/31144 ,  H01L21/3145 ,  H01L21/31625 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/7833 ,  Y10S430/151 ,  Y10S438/952

    摘要： Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface of a substrate. A layer which is transparent to a wavelength of light used during the photolithographic process is provided over the first anti-reflective coating, and a photosensitive material is provided above the transparent layer. The photosensitive material is exposed to a source of radiation including the wavelength of light. Preferably, the first anti-reflective coating extends beneath substantially the entire transparent layer. The complex refractive index of the first anti-reflective coating can be selected to maximize the absorption at the first anti-reflective coating to reduce notching of the photosensitive material.

    摘要翻译： 公开了使用光刻工艺制造器件的技术。 该方法包括在衬底的表面上提供第一抗反射涂层。 在光刻工艺中使用的光的波长透明的层被提供在第一抗反射涂层上，并且感光材料设置在透明层的上方。 感光材料暴露于包括光的波长的辐射源。 优选地，第一抗反射涂层在基本上整个透明层的下方延伸。 可以选择第一抗反射涂层的复合折射率以使第一抗反射涂层处的吸收最大化，以减少光敏材料的凹陷。

    Chemical vapor deposition apparatus and methods
    15.
    发明授权
    Chemical vapor deposition apparatus and methods 有权
    化学气相沉积装置及方法

    公开(公告)号：US07354631B2

    公开(公告)日：2008-04-08

    申请号：US10704315

    申请日：2003-11-06

    申请人： Jeff N. Fuss ,  Kevin T. Hamer ,  Zhiping Yin

    发明人： Jeff N. Fuss ,  Kevin T. Hamer ,  Zhiping Yin

    IPC分类号： H05H1/24 ,  C23C16/00

    CPC分类号： H01J37/3244 ,  C23C16/4404 ,  C23C16/4405

    摘要： This invention includes chemical vapor deposition apparatus, methods of chemical vapor depositing an amorphous carbon comprising layer on a substrate, and methods of chemical vapor depositing at least one of Si3N4 and SixOyNz on a substrate. In certain implementations, a gas output manifold having at least one gas output to a deposition chamber and at least three gas inputs is utilized. In certain implementations, a remote plasma generator is utilized. In certain implementations, at least one cleaning gas input line feeds the remote plasma generator. In certain implementations, the at least one cleaning gas input line includes an amorphous carbon cleaning gas input and an Si3N4 or SixOyNz cleaning gas input.

    摘要翻译： 本发明包括化学气相沉积装置，在衬底上化学气相沉积无定形碳的层的方法，以及化学气相沉积Si 3 N 4 N 3中的至少一种的方法， 和基底上的Si x O x N z N z z。 在某些实施方案中，利用具有至少一个气体输出到沉积室和至少三个气体输入的气体输出歧管。 在某些实施方案中，利用远程等离子体发生器。 在某些实施方案中，至少一个清洁气体输入管线馈送远程等离子体发生器。 在某些实施方案中，所述至少一个清洁气体输入管线包括无定形碳清洁气体输入口和Si 3 N 4 N 4 Si 3 O 4 清洁气体输入。

    Low k interlevel dielectric layer fabrication methods
    19.
    发明授权
    Low k interlevel dielectric layer fabrication methods 失效

    公开(公告)号：US07067415B2

    公开(公告)日：2006-06-27

    申请号：US10205930

    申请日：2002-07-25

    申请人： Weimin Li ,  Zhiping Yin ,  William Budge

    发明人： Weimin Li ,  Zhiping Yin ,  William Budge

    IPC分类号： H01L21/4763 ,  H01L21/31 ,  H01L21/477

    CPC分类号： H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/31633 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828

    摘要： A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide comprising interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is formed over the substrate. After forming the carbon comprising dielectric layer, it is exposed to a plasma comprising oxygen effective to reduce the dielectric constant to below what it was prior to said exposing. A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. In a chamber, an interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is plasma enhanced chemical vapor deposited over the substrate at subatmospheric pressure. After forming the carbon comprising dielectric layer, it is exposed to a plasma comprising oxygen at a subatmospheric pressure effective to reduce the dielectric constant by at least 10% below what it was prior to said exposing. The exposing occurs without removing the substrate from the chamber between the depositing and the exposing, and pressure within the chamber is maintained at subatmospheric between the depositing and the exposing.