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    TRIMMING CIRCUIT FOR CLOCK SOURCE
    11.
    发明申请
    TRIMMING CIRCUIT FOR CLOCK SOURCE 有权
    时钟电路的修正电路

    公开(公告)号：US20130285729A1

    公开(公告)日：2013-10-31

    申请号：US13607734

    申请日：2012-09-09

    Applicant: Xiuqiang Xu ,  Jie Jin ,  Yizhong Zhang

    Inventor： Xiuqiang Xu ,  Jie Jin ,  Yizhong Zhang

    IPC: H03L5/00

    CPC classification number: H03K3/0231 ,  H03B2201/0266 ,  H03K4/502 ,  H03K17/6871 ,  H03K2017/066 ,  H03K2217/0036 ,  H03K2217/0054

    Abstract: A semiconductor trimming circuit includes parallel coupled PMOS devices coupled in parallel with parallel coupled NMOS devices and an additional pair of dummy NMOS devices. The dummy NMOS devices are coupled in parallel with the NMOS devices. A trimming circuit for an internal clock source may be formed with an array of such switches for selecting one or more trimming capacitors of the trimming circuit. Such an array has a low leakage current and permits good trimming linearity.

    Abstract translation: 半导体微调电路包括与并联耦合NMOS器件并联耦合的并联耦合PMOS器件和附加的一对虚设NMOS器件。 虚设NMOS器件与NMOS器件并联耦合。 用于内部时钟源的微调电路可以形成有用于选择微调电路的一个或多个微调电容器的这种开关阵列。 这种阵列具有低泄漏电流并且允许良好的微调线性度。

    CIRCUIT ARRANGEMENT OF A VOLTAGE CONTROLLED OSCILLATOR
    12.
    发明申请
    CIRCUIT ARRANGEMENT OF A VOLTAGE CONTROLLED OSCILLATOR 审中-公开
    电压控制振荡器的电路布置

    公开(公告)号：US20110148536A1

    公开(公告)日：2011-06-23

    申请号：US12971267

    申请日：2010-12-17

    Applicant: Alessandro ITALIA ,  Salvatore Dimartina ,  Calogero Marco Ippolito ,  Giuseppe Palmisano

    Inventor： Alessandro ITALIA ,  Salvatore Dimartina ,  Calogero Marco Ippolito ,  Giuseppe Palmisano

    IPC: H03B5/12 ,  H05K13/00

    CPC classification number: H03B5/1243 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03B5/1268 ,  H03B5/1296 ,  H03B2200/0038 ,  H03B2201/0208 ,  H03B2201/0216 ,  H03B2201/0266 ,  Y10T29/49117

    Abstract: A circuit for a voltage controlled oscillator has a bridge structure including two cross-coupled N-type transistors and two cross-coupled P-type transistors. A current mirror is coupled to the two N-type cross-coupled transistors and configured to generate a bias current. An LC resonator is coupled in parallel between the two cross-coupled N-type transistors and the two P-type cross-coupled transistors. The LC resonator includes two pairs of differential inductors mutually coupled by a mutual inductance coefficient, each pair comprising a first inductor arranged on a respective branch of an external loop, and a second inductor arranged on a respective branch of an internal loop. A first varactor is coupled to a common node and a first branch of the internal loop. A second varactor is coupled to the common node and the second branch of the internal loop.

    Abstract translation: 用于压控振荡器的电路具有包括两个交叉耦合的N型晶体管和两个交叉耦合的P型晶体管的桥结构。 电流镜耦合到两个N型交叉耦合晶体管并且被配置为产生偏置电流。 在两个交叉耦合的N型晶体管和两个P型交叉耦合晶体管之间并联耦合LC谐振器。 LC谐振器包括通过互感系数相互耦合的两对差分电感器，每对包括布置在外部环路的相应分支上的第一电感器和布置在内部环路的相应支路上的第二电感器。 第一变容二极管耦合到公共节点和内部循环的第一分支。 第二变容二极管耦合到公共节点和内部循环的第二分支。

    DIGITAL ADJUSTMENT OF AN OSCILLATOR
    15.
    发明申请
    DIGITAL ADJUSTMENT OF AN OSCILLATOR 审中-公开
    振荡器的数字调整

    公开(公告)号：US20070296511A1

    公开(公告)日：2007-12-27

    申请号：US11761668

    申请日：2007-06-12

    Applicant: Christophe Holuigue ,  Stephan Mechnig

    Inventor： Christophe Holuigue ,  Stephan Mechnig

    IPC: H03L7/00

    CPC classification number: H03K17/6872 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1265 ,  H03B5/1268 ,  H03B2200/005 ,  H03B2201/0266 ,  H03J5/244 ,  H03J2200/01 ,  H03K17/063 ,  H03K17/162 ,  H03L7/099 ,  H03L7/10

    Abstract: The invention concerns the adjustment of an oscillation frequency of an oscillator, in particular the digital coarse adjustment of a PLL oscillator by means of a circuit arrangement comprising at least one pair of capacitors (C, C′), of which first terminals are connected with the oscillator, and second terminals can selectively be connected by means of a switching arrangement with a first reference potential (vss), in order to incorporate the capacitor pair (C, C′) into an oscillating circuit of the oscillator, wherein the circuit arrangement comprises: first FETs (T1, T1′) for the respective connection of the second terminals with the first reference potential (vss), a second FET (T2) for the connection of the second terminals with each other, and third FETs (T3, T3′) for the respective connection of the second terminals with a second reference potential (vdd), which differs from the first reference potential (vss).

    Abstract translation: 本发明涉及振荡器的振荡频率的调整，特别是通过包括至少一对电容器（C，C'）的电路装置对PLL振荡器的数字粗略调整，其中第一端子与 振荡器和第二端子可以通过具有第一参考电位（vss）的开关装置选择性地连接，以便将电容器对（C，C'）并入振荡器的振荡电路中，其中电路装置 包括：用于第二端子与第一参考电位（vss）的相应连接的第一FET（T 1，T 1'），用于连接第二端子的第二FET（T 2）和第三FET （T 3，T 3'），用于与第一参考电位（vss）不同的具有第二参考电位（vdd）的第二端子的相应连接。

    Signal modulated voltage controlled oscillator system
    16.
    发明授权
    Signal modulated voltage controlled oscillator system 有权
    信号调制压控振荡器系统

    公开(公告)号：US07298225B2

    公开(公告)日：2007-11-20

    申请号：US11048151

    申请日：2005-01-31

    Applicant: Bour-Yi Sze ,  Chih-Long Ho ,  Da-Wei Sung

    Inventor： Bour-Yi Sze ,  Chih-Long Ho ,  Da-Wei Sung

    IPC: H03B5/00

    CPC classification number: H03L7/10 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/0266 ,  H03C3/0958 ,  H03J5/244 ,  H03L7/099 ,  H03L2207/06

    Abstract: Improved voltage controlled oscillator (VCO) circuits are disclosed. A symmetrical voltage controlled oscillator (VCO) system according to the embodiments of the present invention comprises a frequency tuning circuit containing one or more varactors for receiving a predetermined tuning signal and a frequency tuning bias signal for altering capacitances of the varactors, a modulation circuit coupled in parallel with the frequency tuning circuit containing one or more varactors for modulating one or more outputs, and a core circuit coupled in a parallel with the tuning circuit and the modulation circuit for providing an oscillation mechanism, wherein the core circuit has an inductance module coupled in a parallel fashion with the frequency tuning circuit and the modulation circuit, wherein circuit elements of the VCO system are symmetrically arranged for increasing oscillation efficiency thereof and the varactors are tuned to deliver the output at an output frequency.

    Abstract translation: 公开了改进的压控振荡器（VCO）电路。 根据本发明的实施例的对称压控振荡器（VCO）系统包括频率调谐电路，其包含用于接收预定调谐信号的一个或多个变容二极管和用于改变变容二极管的电容的频率调谐偏置信号，调制电路耦合 与包含用于调制一个或多个输出的一个或多个变容二极管的频率调谐电路并联，以及与调谐电路并联耦合的核心电路和用于提供振荡机构的调制电路，其中所述核心电路具有耦合的电感模块 与频率调谐电路和调制电路并行地组合，其中VCO系统的电路元件被对称地布置以提高其振荡效率，并且可变电抗器被调谐以输出输出频率。

    Technique for reducing capacitance of a switched capacitor array
    17.
    发明申请
    Technique for reducing capacitance of a switched capacitor array 审中-公开
    降低开关电容阵列电容的技术

    公开(公告)号：US20070247237A1

    公开(公告)日：2007-10-25

    申请号：US11393898

    申请日：2006-03-31

    Applicant: Behnam Mohammadi

    Inventor： Behnam Mohammadi

    IPC: H03B5/12

    CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1265 ,  H03B2201/0266 ,  H03J2200/10

    Abstract: A circuit reducing the capacitance of a switched capacitor array by mitigating switch capacitance. Reducing the effect of switch capacitance increases the frequency range of an inductor-capacitor tank containing the switched capacitor array. A pull-up circuit is coupled between a voltage source and a node. A switched capacitor and a switch are coupled to the node. The pull-up circuit biases the switch to reduce switch junction capacitance when the switch is off. In an example, a pull-up resistor is coupled between the node and a voltage source to bias the switch. In another example, a pull-up switch and pull-up resistor are coupled between the node and a voltage source to bias the switch.

    Abstract translation: 通过减轻开关电容来减小开关电容器阵列的电容的电路。 降低开关电容的影响增加了包含开关电容器阵列的电感器 - 电容器槽的频率范围。 上拉电路耦合在电压源和节点之间。 开关电容器和开关耦合到节点。 当开关关闭时，上拉电路偏置开关以减小开关结电容。 在一个示例中，上拉电阻器耦合在节点和电压源之间以偏置开关。 在另一示例中，上拉开关和上拉电阻耦合在节点和电压源之间以偏置开关。

    Digitally programmable capacitor array
    18.
    发明授权
    Digitally programmable capacitor array 有权

    公开(公告)号：US07245519B2

    公开(公告)日：2007-07-17

    申请号：US11209117

    申请日：2005-08-22

    Applicant: Dale J. McQuirk ,  Michael T. Berens

    Inventor： Dale J. McQuirk ,  Michael T. Berens

    IPC: G11C11/24 ,  H03B5/12

    CPC classification number: H01L27/101 ,  H03B2201/0266 ,  H03J2200/10

    Abstract: A programmable capacitor array does not require separate switching transistors because the capacitors themselves have a switchable capacitance, which capacitors are made in the manner of regular N channel transistors with their source/drains connected to each other. When a logic low is applied to the gate, the capacitance is relatively low and the capacitance is what is commonly called parasitic capacitance. The capacitance increases significantly when a logic high is applied to the gate because the logic high has the effect of inverting the channel. Thus, the capacitor array is made of transistors that themselves have switchable capacitance operated so that no separate switching transistors are required. This allows for construction of an array of unit capacitors to achieve monotonic operation and good linearity using conventional manufacturing of N channel transistors while achieving significant area savings and reduced power consumption.

    Voltage-controlled oscillator, transmitter, and receiver
    19.
    发明申请
    Voltage-controlled oscillator, transmitter, and receiver 失效
    压控振荡器，发射器和接收器

    公开(公告)号：US20070132524A1

    公开(公告)日：2007-06-14

    申请号：US11589774

    申请日：2006-10-31

    Applicant: Yusuke Kishino

    Inventor： Yusuke Kishino

    IPC: H03B5/12

    CPC classification number: H03B5/1231 ,  H03B5/1215 ,  H03B5/1265 ,  H03B2201/0266

    Abstract: A voltage-controlled oscillator includes (i) a first variable-capacity element, (ii) a resonance circuit whose resonance frequency changes in accordance with a control voltage applied to the first variable-capacity element, (iii) a second variable-capacity element connected in parallel with the first variable-capacity element, (iv) resonance frequency range switching means which switches the variation range of the resonance frequency of the resonance circuit by switching the capacity of the second variable-capacity element, and (v) a resonance frequency correction circuit which corrects the resonance frequency in such a manner as to prevent the ratio between resonance frequencies before and after the switching of the variation range from depending on the control voltage.

    Abstract translation: 压控振荡器包括：（i）第一可变容量元件，（ii）谐振频率根据施加到第一可变电容元件的控制电压而变化的谐振电路，（iii）第二可变电容元件 （iv）谐振频率范围切换装置，其通过切换第二可变容量元件的容量来切换谐振电路的谐振频率的变化范围，以及（v）共振 频率校正电路，其以这样的方式校正谐振频率，以防止根据控制电压的变化范围的切换之前和之后的谐振频率之间的比率。

    Controlled oscillator
    20.
    发明授权
    Controlled oscillator 有权
    受控振荡器

    公开(公告)号：US07230504B1

    公开(公告)日：2007-06-12

    申请号：US11216496

    申请日：2005-08-31

    Applicant: Augusto M. Marques ,  Scott D. Willingham

    Inventor： Augusto M. Marques ,  Scott D. Willingham

    IPC: H03B5/00

    CPC classification number: H03B5/1228 ,  H03B5/1212 ,  H03B5/124 ,  H03B5/1265 ,  H03B2201/0266

    Abstract: A controlled oscillator circuit includes an amplifier including a first transistor coupled between a first node and a reference node, and a second transistor coupled between a second node and the reference node. The gate of first transistor and the gate of the second transistor may be cross-coupled. The oscillator may also include one or more variable capacitance circuits coupled between the first node and the second node, each including a first capacitor coupled between the first node and a third node, and a second capacitor coupled between the second node and a fourth node. Each variable capacitance circuit may also include a third, a fourth and a fifth transistor interconnected to selectively couple the first and second capacitors to the reference node. The third, fourth and fifth transistors may be low voltage transistors and the first and the second transistors may be high voltage transistors.

    Abstract translation: 受控振荡器电路包括放大器，其包括耦合在第一节点和参考节点之间的第一晶体管，以及耦合在第二节点和参考节点之间的第二晶体管。 第一晶体管的栅极和第二晶体管的栅极可以是交叉耦合的。 振荡器还可以包括耦合在第一节点和第二节点之间的一个或多个可变电容电路，每个可变电容电路包括耦合在第一节点和第三节点之间的第一电容器，以及耦合在第二节点和第四节点之间的第二电容器。 每个可变电容电路还可以包括互连以将第一和第二电容器选择性地耦合到参考节点的第三，第四和第五晶体管。 第三，第四和第五晶体管可以是低电压晶体管，并且第一和第二晶体管可以是高压晶体管。

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