-
11.发明公开公开(公告)号：US20230399749A1
公开(公告)日：2023-12-14
申请号：US18455941
申请日：2023-08-25
发明人： Bo-Eun PARK , Jooho LEE , Yongsung KIM , Jeonggyu SONG
IPC分类号： C23C16/56 , C23C16/455 , C23C14/58 , C23C16/40 , C01G27/02 , C23C14/08 , H10B51/00 , H10B53/00
CPC分类号： C23C16/56 , C23C16/45525 , C23C14/5806 , C23C16/40 , C01G27/02 , C23C14/08 , H10B51/00 , H10B53/00 , C01P2004/24 , C01P2002/72 , C01P2006/40 , C01P2002/76
摘要： A thin film structure includes a first conductive layer, a dielectric material layer on the first conductive layer, and an upper layer on the dielectric material layer. The dielectric material layer including HfxA1-xO2 satisfies at least one of a first condition and a second condition. In the first condition the dielectric material layer is formed to a thickness of 5 nm or less and in the second condition the x in HfxA1-xO2 is in a range of 0.3 to 0.5.
-
公开(公告)号：US20230395690A1
公开(公告)日：2023-12-07
申请号：US18235740
申请日：2023-08-18
发明人： Albert Liao , Manzar Siddik
CPC分类号： H01L29/516 , G11C11/221 , H01L29/40111 , G11C11/223 , H01L28/65 , H01L28/55 , H01L28/40 , H10B53/00 , H10B53/30 , H01L2924/1441
摘要： Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second electrode and the ferroelectric insulative material. The metal oxide has a thickness of less than or equal to about 30 Å. Some embodiments include a method of forming an assembly. A first capacitor electrode is formed over a semiconductor-containing base. Ferroelectric insulative material is formed over the first electrode. A metal-containing material is formed over the ferroelectric insulative material. The metal-containing material is oxidized to form a metal oxide from the metal-containing material. A second electrode is formed over the metal oxide.
-
公开(公告)号：US11980036B2
公开(公告)日：2024-05-07
申请号：US17873207
申请日：2022-07-26
发明人： Chao-I Wu , Yu-Ming Lin , Han-Jong Chia
CPC分类号： H10B53/00 , G11C5/06 , G11C11/221 , H10B51/00
摘要： A semiconductor structure includes a substrate, an interconnection structure disposed over the substrate and a first memory cell. The first memory cell is disposed over the substrate and embedded in dielectric layers of the interconnection structure. The first memory cell includes a first transistor and a first data storage structure. The first transistor is disposed on a first base dielectric layer and embedded in a first dielectric layer. The first data storage structure is embedded in a second dielectric layer and electrically connected to the first transistor. The first data storage structure includes a first electrode, a second electrode and a storage layer sandwiched between the first electrode and the second electrode.
-
14.发明授权公开(公告)号：US11955153B1
公开(公告)日：2024-04-09
申请号：US17654908
申请日：2022-03-15
发明人： Rajeev Kumar Dokania , Amrita Mathuriya , Debo Olaosebikan , Tanay Gosavi , Noriyuki Sato , Sasikanth Manipatruni
CPC分类号： G11C11/161 , G11C11/221 , H01L25/0652 , H01L28/55 , H01L28/75 , H10B12/20 , H10B12/48 , H10B53/00
摘要： A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.
-
15.发明授权公开(公告)号：US11950429B2
公开(公告)日：2024-04-02
申请号：US17078672
申请日：2020-10-23
发明人： Sanghun Jeon
CPC分类号： H10B53/00 , G11C11/221 , H01L29/516 , H01L29/78391 , H10B53/20
摘要： The present invention relates to ferroelectric capacitors, transistors, memory device, and method of manufacturing ferroelectric devices. The ferroelectric capacitor includes a first electrode, a second electrode facing the first electrode, a ferroelectric layer between the first electrode and the second electrode, and an interfacial layer between the ferroelectric layer and the first electrode or between the ferroelectric layer and the second electrode. The ferroelectric layer includes hafnium-based oxide. The interfacial layer includes HfO2.
-
公开(公告)号：US20240090232A1
公开(公告)日：2024-03-14
申请号：US18511461
申请日：2023-11-16
发明人： Chung-Liang CHENG , Huang-Lin CHAO
IPC分类号： H10B53/20 , H01L23/522 , H01L23/528 , H01L29/423 , H10B51/10 , H10B51/20 , H10B53/00 , H10B53/10
CPC分类号： H10B53/20 , H01L23/5226 , H01L23/5283 , H01L29/42392 , H10B51/10 , H10B51/20 , H10B53/00 , H10B53/10
摘要： A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.
-
公开(公告)号：US20240074206A1
公开(公告)日：2024-02-29
申请号：US18501360
申请日：2023-11-03
发明人： Fu-Chen CHANG , Kuo-Chi TU , Tzu-Yu CHEN , Sheng-Hung SHIH
摘要： A semiconductor device includes a random access memory (RAM) structure and a dielectric layer. The RAM structure is over a substrate and includes a bottom electrode layer, a ferroelectric layer over the bottom electrode layer, and a top electrode layer over the ferroelectric layer. The dielectric layer is over the substrate and laterally surrounds a lower portion of the RAM structure. From a cross-sectional view, the bottom electrode layer of the RAM structure has a lateral portion and a vertical portion, and the vertical portion upwardly extends from the lateral portion to a position higher than a top surface of the dielectric layer.
-
公开(公告)号：US20230284455A1
公开(公告)日：2023-09-07
申请号：US17823433
申请日：2022-08-30
发明人： Gaurav Thareja , Sasikanth Manipatruni , Rajeev Kumar Dokania , Ramamoorthy Ramesh , Amrita Mathuriya
CPC分类号： H10B53/00 , G11C11/221 , H01L28/40
摘要： The memory bit-cell formed using the ferroelectric capacitor results in a taller and narrower bit-cell compared to traditional memory bit-cells. As such, more bit-cells can be packed in a die resulting in a higher density memory that can operate at lower voltages than traditional memories while providing the much sought after non-volatility behavior. The pillar capacitor includes a plug that assists in fabricating a narrow pillar.
-
公开(公告)号：US11727260B2
公开(公告)日：2023-08-15
申请号：US17484828
申请日：2021-09-24
申请人： Intel Corporation
发明人： Abhishek Sharma , Jack T. Kavalieros , Ian A. Young , Ram Krishnamurthy , Sasikanth Manipatruni , Uygar Avci , Gregory K. Chen , Amrita Mathuriya , Raghavan Kumar , Phil Knag , Huseyin Ekin Sumbul , Nazila Haratipour , Van H. Le
IPC分类号： G06N3/063 , H01L27/108 , H01L27/11502 , G06N3/04 , G06F17/16 , H01L27/11 , G11C11/54 , G11C7/10 , G11C11/419 , G11C11/409 , G11C11/22 , G06N3/065 , H10B10/00 , H10B12/00 , H10B53/00
CPC分类号： G06N3/065 , G06F17/16 , G06N3/04 , G11C7/1006 , G11C7/1039 , G11C11/54 , H10B10/18 , H10B12/01 , H10B12/033 , H10B12/20 , H10B12/50 , H10B53/00 , G11C11/221 , G11C11/409 , G11C11/419
摘要： An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.
-
公开(公告)号：US20240363679A1
公开(公告)日：2024-10-31
申请号：US18765887
申请日：2024-07-08
发明人： Boeun PARK , Yongsung KIM , Jeonggyu SONG , Jooho LEE
摘要： An anti-ferroelectric thin-film structure including a dielectric layer including an anti-ferroelectric phase of hafnium oxide; and an inserted layer in the dielectric layer, the inserted layer including an oxide. An electronic device to which the anti-ferroelectric thin-film structure has been applied may secure an operating voltage section with little hysteresis.
-
-
-
-
-
-
-
-
-
搜索结果
41 条记录 (耗时 0.024 秒)
