公开(公告)号：US11829686B2

公开(公告)日：2023-11-28

申请号：US17026009

申请日：2020-09-18

Applicant: Integral Reality Labs, Inc.

Inventor： Baha'Aldeen Abunojaim ,  Muhannad Taslaq ,  Hasan Aadab Alhimish

IPC: G06F30/00 ,  B29C70/04 ,  G06T19/20 ,  G06T19/00 ,  B29C64/386 ,  G06F3/04815 ,  G06F3/04847 ,  G06T17/20 ,  G06F111/02 ,  G06F111/06 ,  G06F113/22 ,  G06F117/02 ,  G06F117/08 ,  G06F119/18

CPC classification number: G06F30/00 ,  B29C64/386 ,  B29C70/04 ,  G06F3/04815 ,  G06F3/04847 ,  G06T17/20 ,  G06T19/003 ,  G06T19/006 ,  G06T19/20 ,  G06F2111/02 ,  G06F2111/06 ,  G06F2113/22 ,  G06F2117/02 ,  G06F2117/08 ,  G06F2119/18

Abstract: A network system can optimize 3D models for 3D printing. A smoothing operation can be performed for a 3D model that comprises a plurality of voxels by identifying exterior voxels of the 3D model. For a first exterior voxel of the 3D model, an exterior surface orientation can be determined and a smoothing operation can be performed based on the determined exterior surface orientation. The smoothing operation can include performing a triangulation operation based on the determined exterior surface orientation of the first exterior voxel. Furthermore, in response to determining that a dimension of a set of voxels is below a threshold limit, one or more voxels can be added to the set of voxels to satisfy the threshold limit.

公开(公告)号：US20230367951A1

公开(公告)日：2023-11-16

申请号：US18359648

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bing-Siang Chao

IPC: G06F30/398 ,  G03F7/00 ,  H01L21/66 ,  G06F111/06 ,  G06F30/30 ,  G06F119/18 ,  G06F119/22

CPC classification number: G06F30/398 ,  G03F7/70433 ,  G03F7/70491 ,  G03F7/7065 ,  H01L22/12 ,  G03F7/705 ,  G03F7/70616 ,  G06F2111/06 ,  G06F30/30 ,  G06F2119/18 ,  G06F2119/22

Abstract: According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.

公开(公告)号：US11762125B2

公开(公告)日：2023-09-19

申请号：US17693158

申请日：2022-03-11

Applicant: CLIMATE LLC

Inventor： Lijuan Xu ,  Ying Xu

IPC: G01V99/00 ,  G01N21/359 ,  G01N33/00 ,  G06Q10/04 ,  G06F30/27 ,  A01B76/00 ,  G01N21/31 ,  G01W1/10 ,  G01N33/24 ,  G01N21/17 ,  A01B79/00 ,  G06F111/06

CPC classification number: G01V99/005 ,  A01B76/00 ,  G01N21/31 ,  G01N21/359 ,  G01N33/0098 ,  G01N33/24 ,  G01W1/10 ,  G06F30/27 ,  G06Q10/04 ,  A01B79/005 ,  G01N2021/1793 ,  G01N2021/3155 ,  G01N2201/0616 ,  G01N2201/129 ,  G06F2111/06

Abstract: A method for determining national crop yields during the growing season is provided. In an embodiment, a server computer system receives agricultural data records for a particular year that represent covariate data values related to plants at a specific geo-location at a specific time. The system aggregates the records to create geo-specific time series for a geo-location over a specified time. The system creates aggregated time series from a subset of the geo-specific time series. The system selects a representative feature from the aggregated time series and creates a covariate matrix for each specific geographic area in computer memory. The system determines a specific crop yield for a specific year using linear regression to calculate the specific crop yield from the covariate matrix. The system determines a forecasted crop yield for the specific year using a sum of the specific crop yields for the specific year, as adjusted.

公开(公告)号：US20220318440A1

公开(公告)日：2022-10-06

申请号：US17220813

申请日：2021-04-01

Applicant: AUTODESK, INC.

Inventor： Damon LAU ,  David BENJAMIN ,  James STODDART ,  Lorenzo VILLAGGI ,  Dale ZHAO

IPC: G06F30/13 ,  G06F111/06 ,  G06F111/04

Abstract: Techniques are disclosed for designing manufacturing facilities. A design application imports a computer-aided design (CAD) model and metadata associated with a manufacturing facility to generate a data set that specifies geometric and manufacturing constraints of the manufacturing facility. The design application performs optimization operations based on the data set to identify one or more high-performing designs that assign components to docks in the manufacturing facility. The optimization operations can include genetic optimization operations that generate multiple generations of designs, each of which is evaluated based on a travel distance, congestion, and number of turns associated with paths traversed by components for the design.

公开(公告)号：US11347926B2

公开(公告)日：2022-05-31

申请号：US17121174

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bing-Siang Chao

IPC: G06F30/398 ,  G03F7/20 ,  H01L21/66 ,  G06F111/06 ,  G06F30/30 ,  G06F119/18 ,  G06F119/22

Abstract: According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.

公开(公告)号：US11301596B2

公开(公告)日：2022-04-12

申请号：US16143998

申请日：2018-09-27

Applicant: AlphaMorph, LLC

Inventor： Matthew Barad ,  Jackson Chen

IPC: G06F30/00 ,  G06N3/12 ,  G06F111/06 ,  G06F111/20

Abstract: An engineering design tool and methods for using the same are disclosed. A method may include receiving at least one parent design and generating a plurality of first-generation design copies that each include a characteristic that has mutated from the parent design. New generations of design copies are successively produced from the additional design copies based on fitness testing the new generations of design copies. Characteristics from intergenerational design copies that are not within the same generation are utilized to perform intergenerational crossover, and a likelihood of a mutation of a design copy is increased in response to a threshold number of generations without an improvement in a fitness score of a design copy. New generations continue to be successively produced until a likelihood that any design copy with a higher fitness score will be produced is below a statistical threshold.

公开(公告)号：US11132476B2

公开(公告)日：2021-09-28

申请号：US15840486

申请日：2017-12-13

Applicant: Facebook, Inc.

Inventor： Dorian Frederic Marie Colas ,  Vishvas Samuel Suryakumar ,  Nicholas Roberts

IPC: G06F30/15 ,  G06F111/06

Abstract: Systems, methods, and non-transitory computer-readable media are disclosed for automatically generating aircraft models by modifying quantitative design variables based on joint analysis of aerodynamic, structural, and/or energy performance. For example, in one or more embodiments, disclosed systems iteratively modify ailerons and a propulsion system based on performance criteria until a balancing metric converges. The disclosed systems then determine performance metrics corresponding to the aircraft model with the modified ailerons and propulsion system, such as stresses and deflections under performance load, a measure of aeroelastic stability, and a battery performance metric. The disclosed systems can then modify design variables based on the determined performance metrics to explore the design space and generate a new aircraft model.

公开(公告)号：US10819270B2

公开(公告)日：2020-10-27

申请号：US15923909

申请日：2018-03-16

Applicant: UCHICAGO ARGONNE, LLC

Inventor： Alex B. Martinson ,  Nari Jeon ,  Stephen K. Gray ,  Jonathan J. Foley, IV

IPC: H02S10/30 ,  H01L31/054 ,  G06F30/20 ,  H01L27/02 ,  H01L33/10 ,  H01L33/46 ,  H01L51/52 ,  G06F30/00 ,  G06F119/08 ,  G06F111/06 ,  G06F119/06 ,  G06F30/337 ,  G06F30/398 ,  G06F9/455 ,  G06F11/36 ,  G06F16/2453 ,  G06F9/48

Abstract: Tailoring the emission spectra of a solar thermophotovoltaic emitter away from that of a blackbody, thereby minimizing transmission and thermalization loss in the energy receiver, is a viable approach to circumventing the Shockley-Queisser limit to single junction solar energy conversion. Embodiments allow for radically tuned selective thermal emission that leverages the interplay between two resonant phenomena in a simple planar structure—absorption in weakly-absorbing thin films and reflection in multi-layer dielectric stacks. A virtual screening approach is employed based on Pareto optimality to identify a small number of promising structures for a selective thermal emitter from a search space of millions, several of which approach the ideal values of a step-function selective thermal emitter.

公开(公告)号：US10810345B2

公开(公告)日：2020-10-20

申请号：US16386608

申请日：2019-04-17

Applicant: International Business Machines Corporation

Inventor： Steven B. Gold ,  Wen Wei Low ,  Feng Xue ,  Yvonne Chii Yeo ,  Jung H. Yoon

IPC: G06F30/398 ,  G06F30/327 ,  G11C29/00 ,  G11C29/44 ,  H01L21/66 ,  G06F30/39 ,  G11C29/04 ,  G06F111/06 ,  G06F115/10 ,  G06F119/18

Abstract: A computer-implemented method modifies a manufacturing process for integrated circuits that include memory chips and a memory buffer. One or more processors identify a performance trending estimate of memory chip failures versus memory buffer failures in failed integrated circuits. The processor(s) identify a location and address of each memory chip in the identified failed integrated circuits that has a memory chip failure. The processor(s) identify a wafer location on a wafer die on which each memory buffer that has a memory buffer failure was formed. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, the location and address of each memory chip in the failed integrated circuits, and the wafer location on the wafer die on which each memory buffer that has the memory buffer failure was formed such that a manufacturing process for the integrated circuits is modified based on the FA pareto.

公开(公告)号：US10678973B2

公开(公告)日：2020-06-09

申请号：US15724663

申请日：2017-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin Chuang ,  Ching-Fang Chen ,  Wei-Li Chen ,  Wei-Pin Changchien ,  Yung-Chin Hou ,  Yun-Han Lee

IPC: G06F17/50 ,  G06N20/00 ,  H01L27/00 ,  G06F30/27 ,  G06F30/30 ,  G06F30/3308 ,  G06F30/337 ,  G06F30/373 ,  H01L27/02 ,  H05K3/00 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  H01L27/118 ,  G06F30/367 ,  G06F111/06 ,  G06F111/02 ,  G06F119/22

Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs. The EDA of the present disclosure can substitute the one or more electronic architectural models before, during, and/or after designing, simulating, analyzing, and/or verifying of the one or more electronic architectural designs to effectively decrease the time to market (TTM) for the electronic device.