公开(公告)号：US3772100A

公开(公告)日：1973-11-13

申请号：US3772100D

申请日：1971-06-30

Applicant: DENKI ONKYO CO LTD

Inventor： MASUDA N ,  NISHINO Y ,  KASE H

IPC: H01L21/285 ,  H01L21/316 ,  H01L23/482 ,  H01L1/00

CPC classification number: H01L21/28575 ,  H01L21/31654 ,  H01L23/4824 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A method for forming a plurality of metal strips on a semiconductor device comprising forming a metallic layer on a surface of semiconductor base, coating a photo sensitive resin layer on the said surface of the metallic layer, forming at least one pattern corresponding to at least one metal strip on the sensitized resin layer and etching the metallic layer with an etching solution which oxidizes the semiconductor base.

Abstract translation: 一种用于在半导体器件上形成多个金属条的方法，包括在半导体基底的表面上形成金属层，在所述金属层的所述表面上涂覆感光树脂层，形成至少一个与至少一个 在敏化树脂层上的金属条，并用蚀刻半导体基底的蚀刻溶液蚀刻金属层。

公开(公告)号：US3460002A

公开(公告)日：1969-08-05

申请号：US3460002D

申请日：1965-09-29

Applicant: MICROWAVE ASS

Inventor： MESLER LARRY L

IPC: H01L23/31 ,  H01L29/00 ,  H01L9/00 ,  H01L1/00 ,  H05K5/02

CPC classification number: H01L23/3157 ,  H01L29/00 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：US08193655B2

公开(公告)日：2012-06-05

申请号：US13044781

申请日：2011-03-10

Applicant: Allan Roberts ,  Weixing Lu

Inventor： Allan Roberts ,  Weixing Lu

IPC: F03B13/12 ,  H01L1/00

CPC classification number: F03B13/14 ,  H01L41/22 ,  Y02E10/38 ,  Y10T29/42

Abstract: One embodiment of the present invention consists of a system of small, interconnected cubes, each containing interior walls made from a highly sensitive multi-layer piezoelectric material and each having heavy mass, such as stainless steel, inside the cube interior. An elastic material layer covers the heavy internal mass that is in contact with the piezoelectric cube walls. As the system moves with the water, the heavy mass inside each cube exerts varying inertial forces on the cube walls causing a piezoelectric current to be generated. However, the cell walls may also be constructed using commercially available piezoelectric materials. This approach is a second embodiment of the current invention and includes the same system design as the first embodiment except that the internal cubic cell walls are fabricated in a unique manner using commercially available piezoelectric materials, rather than the non-central symmetric LB poly-vinylidene fluoride (PVDF) multilayer piezoelectric material.

Abstract translation: 本发明的一个实施例由小型互连的立方体组成，每个立方体包含由高灵敏度的多层压电材料制成的内壁，并且每个都具有重质量，例如不锈钢，在立方体内部。 弹性材料层覆盖与压电立方体壁接触的重质内部质量。 随着系统随水流动，每个立方体内的重质量块在立方体壁上施加不同的惯性力，导致产生压电电流。 然而，细胞壁也可以使用市售的压电材料构造。 该方法是本发明的第二实施例，并且包括与第一实施例相同的系统设计，除了使用市售的压电材料而不是非中心对称LB聚偏亚乙烯以独特的方式制造内部立方晶胞壁 氟化物（PVDF）多层压电材料。

公开(公告)号：US06905548B2

公开(公告)日：2005-06-14

申请号：US10378496

申请日：2003-03-03

Applicant: Holger Jürgensen ,  Gerhard Karl Strauch ,  Johannes Käppeler

Inventor： Holger Jürgensen ,  Gerhard Karl Strauch ,  Johannes Käppeler

IPC: C23C16/44 ,  C30B25/02 ,  C30B25/14 ,  C23C16/00 ,  H01L1/00

CPC classification number: C23C16/45561 ,  C23C16/4401 ,  C30B25/02 ,  C30B25/14

Abstract: The invention relates to a device for the deposition of in particular, crystalline layers on one or several, in particular, equally crystalline substrates, comprising a process chamber, arranged in a reactor housing, which may be charged with the substrates from above, by a reactor housing opening which may be sealed by a cover. The reactor housing opening opens out into a glove box, in particular flushed with highly pure gas and connects electricity, liquid or gas supply lines to the cover. According to the invention, the connection of supply lines for electricity, fluid or gas sources arranged outside the glove box to the cover of the reactor housing arranged within the glove box may be improved, whereby the electricity, fluid or gas supply lines run freely, from outside the glove box, through a flexible tube which is sealed atone end to a flange arrangement rigidly fixed to the cover and sealed at the other end to an opening in the glove box wall.

Abstract translation: 本发明涉及一种用于特别沉积在一个或多个特别是同等结晶的基底上的结晶层的装置，其包括设置在反应器壳体中的处理室，该反应器壳体可以从上方装入基板，通过 反应器壳体开口，其可由盖子密封。 反应器壳体开口打开到手套箱中，特别是用高纯度气体冲洗并将电力，液体或气体供应管线连接到盖子上。 根据本发明，可以改善布置在手套箱外部的用于电力，流体或气体源的供给管线与布置在手套箱内的反应堆壳体的盖的连接，由此电力，流体或气体供应管线自由运行， 从手套箱的外部通过柔性管，该柔性管在一端被密封到刚性地固定到盖上并且在另一端被密封在手套箱壁中的开口的凸缘装置。

公开(公告)号：US6037278A

公开(公告)日：2000-03-14

申请号：US920906

申请日：1997-08-29

Applicant: Ken-Ichi Koyanagi ,  Koji Kishimoto

Inventor： Ken-Ichi Koyanagi ,  Koji Kishimoto

IPC: H01L21/31 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L1/00

CPC classification number: H01L21/76843 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76837

Abstract: Disclosed is a method of manufacturing a semiconductor device aimed at improving reliability of wiring, more particularly, of a via hole when a silicon oxide film formed by a high density plasma CVD process is used as an inter-level dielectric film in an integrated circuit having a multi-level wiring structure. When the multi-level wiring structure is formed on a semiconductor substrate, after underlying wiring is formed, a silicon oxide film is formed on the entire surface of the substrate by a high density plasma CVD process, and heat treated in inert gas or oxygen atmosphere at a temperature of 300.degree. C. or more but 500.degree. C. or less for 10 minutes or more. Excess hygrogen incorporated in the silicon oxide during the CVD process is removed by the above heat treatment. Subsequently, via holes are opened, and upper wiring is formed.

Abstract translation: 公开了一种制造半导体器件的方法，该方法旨在提高布线的可靠性，特别是在通过高密度等离子体CVD工艺形成的氧化硅膜作为集成电路中的级间电介质膜时使用通路孔， 多层布线结构。 当在半导体衬底上形成多层布线结构时，在形成底层布线之后，通过高密度等离子体CVD工艺在衬底的整个表面上形成氧化硅膜，并在惰性气体或氧气气氛中进行热处理 在300℃以上但500℃​​以下的温度下进行10分钟以上。 通过上述热处理除去CVD过程中掺入氧化硅中的过量氢。 随后，打开通孔，形成上部布线。

公开(公告)号：US6001730A

公开(公告)日：1999-12-14

申请号：US954191

申请日：1997-10-20

Applicant: Janos Farkas ,  Rajeev Bajaj ,  Melissa Freeman ,  David K. Watts ,  Sanjit Das

Inventor： Janos Farkas ,  Rajeev Bajaj ,  Melissa Freeman ,  David K. Watts ,  Sanjit Das

IPC: C09G1/02 ,  H01L21/321 ,  H01L21/768 ,  H01L1/00

CPC classification number: H01L21/76873 ,  C09G1/02 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877

Abstract: A method for forming a copper interconnect on an integrated circuit (IC) begins by forming a dielectric layer (20) having an opening. A tantalum-based barrier layer (21), such as TaN or TaSiN, is formed within the opening in the layer (20). A copper layer (22) is formed over the barrier layer (21). A first CMP process is used to polish the copper (22) to expose portions of the barrier (21). A second CMP process which is different from the first CMP process is then used to polish exposed portions of the layer (21) faster than the dielectric layer (20) or the copper layer (22). After this two-step CMP process, a copper interconnect having a tantalum-based barrier is formed across the integrated circuit substrate (12).

Abstract translation: 在集成电路（IC）上形成铜互连的方法通过形成具有开口的电介质层（20）开始。 在层（20）的开口内形成有TaN或TaSiN等钽系阻挡层（21）。 在阻挡层（21）的上方形成铜层（22）。 第一CMP工艺用于抛光铜（22）以暴露阻挡层（21）的部分。 然后使用与第一CMP工艺不同的第二CMP工艺来比电介质层（20）或铜层（22）更快地抛光层（21）的暴露部分。 在该两步CMP工艺之后，跨越集成电路基板（12）形成具有钽基阻挡层的铜互连。

公开(公告)号：US5828096A

公开(公告)日：1998-10-27

申请号：US726314

申请日：1996-10-02

Applicant: Yoshikazu Ohno ,  Hiroki Shinkawata ,  Takahiro Yokoi

Inventor： Yoshikazu Ohno ,  Hiroki Shinkawata ,  Takahiro Yokoi

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522 ,  H01L27/108 ,  H01L1/00

CPC classification number: H01L23/5226 ,  H01L23/485 ,  H01L2924/0002

Abstract: A semiconductor device appropriate for increased integrity in which occurrence of electrical short-circuit between a conductor for connecting a bit line and a semiconductor substrate and a gate electrode is obtained. In this semiconductor device, a first insulation layer, a second insulation layer, and a third insulation layer are formed between a first interconnection layer on the semiconductor substrate and a second interconnection layer. The etching rates of the first insulation layer and the second insulation layer are lower than the etching rate of the third insulation layer.

Abstract translation: 一种半导体装置，其适用于提高连接位线用导体与半导体基板与栅电极之间发生电短路的完整性。 在该半导体器件中，在半导体衬底上的第一互连层和第二互连层之间形成第一绝缘层，第二绝缘层和第三绝缘层。 第一绝缘层和第二绝缘层的蚀刻速率低于第三绝缘层的蚀刻速率。

公开(公告)号：US5789265A

公开(公告)日：1998-08-04

申请号：US799634

申请日：1997-02-12

Applicant: Koichi Nitta ,  Sumio Ishimatsu

Inventor： Koichi Nitta ,  Sumio Ishimatsu

IPC: H01L33/00 ,  H01S5/323 ,  H01L1/00

CPC classification number: H01L33/007 ,  H01S5/32341

Abstract: A method of manufacturing blue light-emitting device is disclosed wherein a laminated structure comprising a p-type In.sub.x Al.sub.y Ga.sub.1-x-y N layer and an n-type In.sub.x Al.sub.y Ga.sub.1-x-y N layer are etched selectively by virtue of a parallel plate type plasma etching (RIE) using etching gas including boron trichloride (BCl.sub.3) and chlorine (Cl.sub.2).

Abstract translation: 公开了一种制造蓝色发光器件的方法，其中通过平行板型等离子体蚀刻选择性地蚀刻包括p型In x Al y Ga 1-x-y N层和n型In x Al y Ga 1-x-y N层的层压结构 RIE），使用包括三氯化硼（BCl 3）和氯（Cl 2）的蚀刻气体。

公开(公告)号：US3904540A

公开(公告)日：1975-09-09

申请号：US37063373

申请日：1973-06-18

Applicant: PFIZER

Inventor： BENNETCH LEONARD M ,  GREINER HARRY S ,  HANCOCK KENNETH R ,  HOFFMAN MARK

IPC: C01G49/06 ,  G11B5/70 ,  G11B5/706 ,  H01L1/00 ,  H01L1/22

CPC classification number: G11B5/70663 ,  C01G49/06 ,  C01P2004/10 ,  C01P2004/51 ,  C01P2004/54 ,  C01P2004/61 ,  C01P2006/40 ,  C01P2006/42 ,  G11B5/70 ,  G11B5/70647 ,  G11B5/70652

Abstract: A magnetic impulse record member comprising a binding medium and synthetic magnetic gamma ferric oxide, said member having an orientation ratio of at least 2.4 in a 1000 oersted field, said ferric oxide produced from synthetic lepidocrocite by coating same with at least one 8-24 carbon atom hydrophobic aliphatic monocarboxylic acid, reducing and oxidizing the coated lepidocrocite, and mechanically densifying the gamma ferric oxide product, said synthetic lepidocrocite having very fine-grained, needle-like crystalline particles at least 70 percent of which have a length to width ratio greater than 10:1 and a length up to 2 microns.

Abstract translation: 一种磁脉冲记录元件，包括粘结介质和合成磁性γ氧化铁，所述元件在1000奥斯特菲尔德场中具有至少2.4的取向比，所述氧化铁由合成的石灰石产生，通过用至少一种8-24碳 原子疏水性脂族单羧酸，还原和氧化涂覆的lepidocrocite，以及机械致密化γ氧化铁产物，所述合成的lepidococite具有非常细粒度的针状结晶颗粒，其至少70％的长宽比大于 10：1，长度可达2微米。

公开(公告)号：US3609475A

公开(公告)日：1971-09-28

申请号：US3609475D

申请日：1970-05-04

Applicant: HEWLETT PACKARD CO

Inventor： KAPOSHILIN GEORGE N

IPC: H01L33/52 ,  H01L33/62 ,  H01L1/00

CPC classification number: H01L33/62 ,  H01L24/97 ,  H01L33/52 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/12041 ,  H01L2924/00014

Abstract: A light-emitting diode (LED) is bonded to a pair of metal leads which are attached to a metal lead frame with a plurality of lead pairs, such that its optical axis is parallel to the longitudinal axis of the leads. The device so formed is encapsulated in two colors of plastic, a clear portion over the diode to transmit light from the diode and a dark portion behind the diode to improve the diode on-off contrast and make a hermetic seal with the leads. After encapsulation individual devices are separated from each other by cutting the leads from the lead frame.