公开(公告)号：US06531340B2

公开(公告)日：2003-03-11

申请号：US09790527

申请日：2001-02-23

Applicant: Tongbi Jiang

Inventor： Tongbi Jiang

IPC: H01L2144

CPC classification number: H01L24/83 ,  C09J5/00 ,  C09J5/06 ,  C09J11/00 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  Y10T428/249921 ,  Y10T428/3167 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An apparatus and method is provided for forming a board-on-chip (BOC) package. An adhesive material including a carrier and microcapsules distributed in the carrier is used to bond a semiconductor component to a mounting surface in a BOC package. The microcapsules contain a hardener and/or a catalyst that, when combined with the carrier, initiate a bonding reaction. The contents of the microcapsules are released via application of an external influence, such as pressure or heat, when the bonding reaction is desired to begin. The use of microcapsules permits the formulation of adhesive blends with a substantially increased pot life, increased stability and reliability at high temperatures, and favorable low temperature reaction and bonding characteristics.

公开(公告)号：US06520030B1

公开(公告)日：2003-02-18

申请号：US09531166

申请日：2000-03-21

Applicant: Tongbi Jiang ,  Zhiqiang Wu

Inventor： Tongbi Jiang ,  Zhiqiang Wu

IPC: G01L516

CPC classification number: G01L1/205

Abstract: A high-resolution pressure-sensing device is disclosed. The device includes an insulating flexible matrix having a plurality of filler particles. Application of a force to the matrix causes compression of the matrix. This results in the filler particles occupying a greater amount of space within the matrix relative to when no force is applied. A detector attached to the matrix detects or measures the volume of the filler particles relative to the volume of the matrix, and therefore determines the force applied to the matrix. Preferably, the resistivity of the matrix is inversely proportional to the volume percent of the filler particles, in which case the detector is a resistance-measuring circuit.

Abstract translation: 公开了一种高分辨率压力感测装置。 该装置包括具有多个填料颗粒的绝缘柔性基质。 对矩阵施加力会导致矩阵的压缩。 这导致在没有施加力的情况下，填料颗粒在基质内占据更大量的空间。 连接到基体的检测器检测或测量填料颗粒相对于基体体积的体积，因此确定施加到基质上的力。 优选地，基质的电阻率与填料颗粒的体积百分比成反比，在这种情况下，检测器是电阻测量电路。

公开(公告)号：US06518094B2

公开(公告)日：2003-02-11

申请号：US09866641

申请日：2001-05-30

Applicant: Tongbi Jiang ,  Alan G. Wood

Inventor： Tongbi Jiang ,  Alan G. Wood

IPC: H01L2144

CPC classification number: H01L23/4985 ,  H01L21/4853 ,  H01L23/49816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A center bond flip-chip device carrier and a method for making and using it are described. The carrier includes a flexible substrate supporting a layer of conductive material and a layer of elastomeric material. At least one pocket is formed in the layer of elastomeric material and sized and shaped to house a solder ball. The solder ball is electrically connected to a die positioned on the layer of elastomeric material and also electrically connected to the layer of conductive material.

公开(公告)号：US06514795B1

公开(公告)日：2003-02-04

申请号：US09974192

申请日：2001-10-10

Applicant: Tongbi Jiang ,  Michael E. Connell

Inventor： Tongbi Jiang ,  Michael E. Connell

IPC: H01L2144

CPC classification number: H01L21/6836 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/274 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A method of packaging semiconductor devices is described. In one embodiment, the method comprises providing a section of wafer mount tape, applying an adhesive layer to the wafer mount tape, stretching the wafer mount tape and the adhesive layer, attaching a wafer to the stretched adhesive layer, cutting the wafer and the adhesive layer, the wafer being cut into a plurality of die, and curing the wafer mount tape. In further embodiments, the method comprises removing at least one of the plurality of die from the wafer mount tape, the removed die having a portion of the adhesive layer coupled thereto, providing a die having a plurality of wire bonds coupled thereto, and coupling the adhesive layer on the removed die to the die having the wire bonds coupled thereto. In another aspect, the present invention is directed to a plurality of stacked semiconductor devices that comprise a first die, the first die having an upper surface, a second die positioned above the first die, the second die having a bottom surface, and an adhesive layer positioned between and coupled to each of the first die and the second die, the adhesive layer comprised of first and second surfaces, the first surface of the adhesive layer being coupled to the bottom surface of the second die thereby defining a first contact area, the second surface of the adhesive layer being coupled to the upper surface of the first die thereby defining a second contact area, the second contact area being less than the first contact area.

Abstract translation: 描述了一种封装半导体器件的方法。 在一个实施例中，该方法包括提供晶片安装带的一部分，向晶片安装带施加粘合剂层，拉伸晶片安装带和粘合剂层，将晶片连接到拉伸的粘合剂层，切割晶片和粘合剂 将晶片切割成多个模具，并固化晶片安装带。 在另外的实施例中，该方法包括从晶片安装带去除多个管芯中的至少一个，所述移除的管芯具有与其连接的粘合层的一部分，提供具有多个与其连接的引线接合的管芯， 将去除的芯片上的粘合剂层连接到具有与其结合的引线键合的管芯。 在另一方面，本发明涉及多个层叠的半导体器件，其包括第一裸片，第一裸片具有上表面，第二裸片位于第一裸片上，第二片具有底表面，以及粘合剂 层，其定位在第一模具和第二模具中的每一个之间并且耦合到第一模具和第二模具中，粘合剂层由第一和第二表面组成，粘合剂层的第一表面耦合到第二模具的底表面，从而限定第一接触区域， 粘合剂层的第二表面耦合到第一模具的上表面，从而限定第二接触区域，第二接触区域小于第一接触区域。

公开(公告)号：US06489681B2

公开(公告)日：2002-12-03

申请号：US09849037

申请日：2001-05-04

Applicant: Tongbi Jiang ,  Syed S. Ahmad

Inventor： Tongbi Jiang ,  Syed S. Ahmad

IPC: H01L2348

CPC classification number: H01L24/12 ,  H01L21/56 ,  H01L23/24 ,  H01L23/4951 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/83191 ,  H01L2224/92147 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K1/095 ,  H05K3/12 ,  H05K3/305 ,  H05K3/321 ,  H05K2203/1563 ,  H05K2203/159 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method of forming high definition elements for electrical and electronic devices, substrates, and other components from or including viscous material. The method includes inverting the electrical components after the viscous material is applied and maintaining the inverted orientation until the viscous material dries or cures enough to maintain definition of its perimeter and edge characteristics.

Abstract translation: 从粘性材料形成或包括粘性材料的电气和电子器件，衬底和其它部件的高清晰度元件的方法。 该方法包括在施加粘性材料之后倒置电气部件并保持反向取向，直到粘性材料干燥或固化足够，以保持其周长和边缘特性的定义。

公开(公告)号：US06452271B2

公开(公告)日：2002-09-17

申请号：US09127041

申请日：1998-07-31

Applicant: Tongbi Jiang ,  Li Li

Inventor： Tongbi Jiang ,  Li Li

IPC: H01L2348

CPC classification number: H01L24/16 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/4846 ,  H01L23/498 ,  H01L24/11 ,  H01L2224/05124 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  Y10S257/913 ,  H01L2924/00014

Abstract: A multi-layered metal bond pad for a semiconductor die having a conductive metal layer and an overlying ruthenium electrode layer. The ruthenium electrode layer protects the conductive metal from oxidation due to ambient environmental conditions. An interconnect structure such as a wire bond or solder ball may be attached to the ruthenium layer to connect the semiconductor die to a lead frame or circuit support structure. Also disclosed are processes for forming the ruthenium layer.

Abstract translation: 一种用于具有导电金属层和上覆钌电极层的半导体管芯的多层金属焊盘。 钌电极层保护导电金属免受周围环境条件的氧化。 诸如引线接合或焊球的互连结构可以附着到钌层，以将半导体管芯连接到引线框架或电路支撑结构。 还公开了形成钌层的方法。

公开(公告)号：US06414869B1

公开(公告)日：2002-07-02

申请号：US09614639

申请日：2000-07-12

Applicant: David Y. Kao ,  Tongbi Jiang

Inventor： David Y. Kao ,  Tongbi Jiang

IPC: G11C506

CPC classification number: G11C5/06 ,  G11C5/04 ,  H05K1/117 ,  H05K1/141 ,  H05K1/148 ,  H05K3/36 ,  H05K3/361 ,  H05K3/366 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: A quad in-line memory module (QIMM) includes a circuit board having top and bottom edge connectors and a number of memory devices mounted on each side of the circuit board. Generally, half of the memory devices are electrically connected to the bottom edge's connector and half are electrically connected to the bottom edge's connector. One edge of the QIMM can be connect directly to a computer system's memory bus. The other edge can be connected to operated as a cache memory or a video memory.

Abstract translation: 四行在线存储器模块（QIMM）包括具有顶部和底部边缘连接器以及安装在电路板的每一侧上的多个存储器件的电路板。 通常，一半的存储器件电连接到底部边缘的连接器，一半存储器件电连接到底部边缘的连接器。 QIMM的一个边缘可以直接连接到计算机系统的内存总线。 另一边可连接作为高速缓冲存储器或视频存储器。

公开(公告)号：US06406944B2

公开(公告)日：2002-06-18

申请号：US09859323

申请日：2001-05-16

Applicant: Tongbi Jiang

Inventor： Tongbi Jiang

IPC: H01L2148

CPC classification number: H01L24/02 ,  H01L2224/0401 ,  H01L2224/45144 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/00

Abstract: The present invention is directed toward an apparatus and method of reinforcement of lead bonding in microelectronics packages. In one embodiment, a microelectronics package includes a microelectronics device having a bond pad, a conductive lead having a first end bonded to the bond pad to form a lead bond, an encapsulating material at least partially disposed about the conductive lead, and a reinforcement portion at least partially disposed about the lead bond and at least partially coupling the first end to the bond pad. The reinforcement portion has a greater modulus of elasticity and/or a greater bond strength than the encapsulating material. During thermal cycling of the microelectronics package, bond liftoff due to CTE mismatch is prevented by the reinforcement portion The reinforcement portion may include a non-conductive adhesive material that physically secures the conductive lead to the bond pad, or alternately, an electrically conductive adhesive material that both physically and/or electrically couples the conductive lead to the bond pad. In an alternate embodiment, a microelectronics package includes a microelectronics device, an interposer, a plurality of conductive leads and a plurality of bond pads, and the reinforcement portion is disposed about a plurality of lead bonds. In this embodiment, the reinforcement portion may include a non-conductive adhesive material, or an anisotropically conductive material.

Abstract translation: 本发明涉及一种在微电子封装中增强引线键合的装置和方法。 在一个实施例中，微电子封装包括具有接合焊盘的微电子器件，具有接合到接合焊盘以形成引线接合的第一端的导电引线，至少部分地布置在导电引线周围的封装材料，以及加强部分 至少部分地围绕所述引线键设置并且至少部分地将所述第一端耦合到所述接合焊盘。 加强部分具有比封装材料更大的弹性模量和/或更大的粘结强度。 在微电子封装的热循环期间，通过加强部分防止由于CTE失配引起的结合剥离。加强部分可以包括非导电粘合材料，其将导电引线物理地固定到接合焊盘，或者替代地，导电粘合材料 物理和/或电耦合导电引线到接合焊盘。 在替代实施例中，微电子封装包括微电子器件，插入器，多个导电引线和多个接合焊盘，并且加强部分围绕多个引线键设置。 在该实施例中，加强部分可以包括非导电粘合材料或各向异性导电材料。

公开(公告)号：US06380632B1

公开(公告)日：2002-04-30

申请号：US09571721

申请日：2000-05-15

Applicant: Tongbi Jiang ,  Alan G. Wood

Inventor： Tongbi Jiang ,  Alan G. Wood

IPC: H01L2348

CPC classification number: H01L23/4985 ,  H01L21/4853 ,  H01L23/49816 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A center bond flip-chip device carrier and a method for making and using it are described. The carrier includes a flexible substrate supporting a layer of conductive material and a layer of elastomeric material. At least one pocket is formed in the layer of elastomeric material and sized and shaped to house a solder ball. The solder ball is electrically connected to a die positioned on the layer of elastomeric material and also electrically connected to the layer of conductive material.

Abstract translation: 描述了一种中心键倒装芯片器件及其制造和使用方法。 载体包括支撑导电材料层和弹性体材料层的柔性基底。 在弹性体材料层中形成至少一个口袋，其尺寸和形状设置成容纳焊球。 焊球电连接到位于弹性体材料层上的模具，并且还电连接到导电材料层。

公开(公告)号：US06355504B1

公开(公告)日：2002-03-12

申请号：US09599161

申请日：2000-06-21

Applicant: Tongbi Jiang

Inventor： Tongbi Jiang

IPC: H01L2144

CPC classification number: H01L24/83 ,  H01L24/16 ,  H01L24/28 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13016 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29499 ,  H01L2224/81141 ,  H01L2224/81903 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/14 ,  H01R4/04 ,  H05K1/111 ,  H05K3/323 ,  H05K2201/09745 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The present invention includes electrical interconnections, methods of conducting electricity, and methods of reducing horizontal conductivity within an anisotropic conductive adhesive. In one embodiment, an electrical interconnection configured to electrically couple a first substrate and a second substrate includes: a bond pad of the first substrate having a male configuration; and a bond pad of the second substrate having a female configuration, the bond pad of the second substrate being configured to mate with the bond pad of the first substrate during electrical connection of the bond pads of the first substrate and the second substrate. A method of conducting electricity according to the present invention includes providing first and second bond pads individually defining a planar dimension; coupling the first and second bond pads at an interface having a surface area greater than the area of the planar dimension; and conducting electricity between the first and second bond pads following the coupling.

Abstract translation: 本发明包括电互连，导电方法以及降低各向异性导电粘合剂内水平电导率的方法。 在一个实施例中，配置成电耦合第一衬底和第二衬底的电互连包括：具有阳构造的第一衬底的接合焊盘; 以及具有凹形结构的所述第二基板的接合焊盘，所述第二基板的接合焊盘被配置为在所述第一基板和所述第二基板的接合焊盘的电连接期间与所述第一基板的接合焊盘配合。 根据本发明的导电方法包括提供单独限定平面尺寸的第一和第二接合焊盘; 在具有大于所述平面尺寸的面积的表面积的界面处耦合所述第一和第二接合焊盘; 并且在耦合之后在第一和第二接合焊盘之间传导电力。