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    EFFECTING SELECTIVITY OF SILICON OR SILICON-GERMANIUM DEPOSITION ON A SILICON OR SILICON-GERMANIUM SUBSTRATE BY DOPING
    202.
    发明申请
    EFFECTING SELECTIVITY OF SILICON OR SILICON-GERMANIUM DEPOSITION ON A SILICON OR SILICON-GERMANIUM SUBSTRATE BY DOPING 有权
    通过掺杂对硅或硅 - 锗基底上的硅或硅 - 锗沉积的选择性进行了研究

    公开(公告)号：US20130240999A1

    公开(公告)日：2013-09-19

    申请号：US13872478

    申请日：2013-04-29

    Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  NXP B.V.

    Inventor： Alexandre Mondot ,  Markus Mueller ,  Thomas Kormann

    IPC: H01L21/8238 ,  H01L27/092

    CPC classification number: H01L21/823814 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823828 ,  H01L27/0922 ,  H01L29/4933 ,  H01L29/4975

    Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. Several devices are, thus, provided. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.

    Abstract translation: 在Si或SiGe表面上选择性沉积Si或SiGe的方法根据第一和第二表面区域的掺杂差异来利用物理化学表面行为的差异。 通过提供具有适当浓度范围的硼掺杂的至少一个第一表面区域，并且在低于或等于800℃的温度下在预烘烤步骤中将衬底表面暴露于清洁和钝化环境气氛，随后的沉积步骤 Si或SiGe不会导致第一表面区域中的层沉积。 该效应用于在不掺杂硼的合适浓度范围内或掺杂有另一掺杂剂的第二表面区域中选择性沉积Si或SiGe，或不掺杂。 因此，提供了几个设备。 因此，该方法节省了根据现有技术在第二表面区域中选择性沉积Si或SiGe所需的常规光刻序列。

    METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT COMPRISING VIAS CROSSING THE SUBSTRATE
    203.
    发明申请
    METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT COMPRISING VIAS CROSSING THE SUBSTRATE 有权
    用于制造包括VIAS跨越基板的集成电路的方法

    公开(公告)号：US20130207279A1

    公开(公告)日：2013-08-15

    申请号：US13766925

    申请日：2013-02-14

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Mohamed BOUCHOUCHA ,  Laurent-Luc Chapelon

    IPC: H01L21/768 ,  H01L23/48

    CPC classification number: H01L21/768 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/16146 ,  H01L2924/13091 ,  H01L2924/00

    Abstract: A method for forming an integrated circuit including the steps of: forming electronic capponents on a first surface of a substrate; forming a stack of interconnection levels on the first surface, each interconnection level including conductive tracks separated by an insulating material; forming at least one hole from a second surface of the substrate, opposite to the first surface, the hole stopping on one of the conductive tracks; depositing, on the walls and the bottom of the hole, a conductive layer and filling the remaining space with a filling material; and forming, in an interconnection level or at the surface of the interconnection stack, and opposite to said at least one hole, at least one region of a material having a modulus of elasticity greater than 50 GPa and an elongation at break greater than 20%, insulated from the conductive tracks.

    Abstract translation: 一种用于形成集成电路的方法，包括以下步骤：在基板的第一表面上形成电子支撑件; 在所述第一表面上形成一叠互连层，每个互连层包括由绝缘材料隔开的导电轨道; 从所述基板的与所述第一表面相对的第二表面形成至少一个孔，所述孔在所述导电轨道中的一个上停止; 在孔的壁和底部上沉积导电层并用填充材料填充剩余的空间; 以及在所述互连叠层的互连层或所述表面上形成并与所述至少一个孔相对的材料的至少一个区域，其弹性模量大于50GPa，断裂伸长率大于20％ ，与导电轨道绝缘。

    DMOS TRANSISTOR ON SOI
    205.
    发明申请
    DMOS TRANSISTOR ON SOI 审中-公开
    SOI上的DMOS晶体管

    公开(公告)号：US20130105893A1

    公开(公告)日：2013-05-02

    申请号：US13660681

    申请日：2012-10-25

    Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

    Inventor： David Petit ,  Bruno Rauber

    IPC: H01L27/088 ,  H01L21/336

    CPC classification number: H01L29/7824 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66689

    Abstract: A DMOS on SOI transistor including an elongated gate extending across the entire width of an active area; a drain region of a first conductivity type extending across the entire width of the active area; a source region of the first conductivity type extending parallel to the gate and stopping before the limit of the active area at least on one side of the transistor width, an interval existing between the limit of the source region and the limit of the active area; a bulk region of a second conductivity type extending under the gate and in said interval; a more heavily-doped region of the second conductivity type extending on a portion of said interval on the side of the limit of the active area; and an elongated source metallization extending across the entire width of the active area.

    Abstract translation: SOI晶体管上的DMOS，包括延伸跨有效区域的整个宽度的细长栅极; 在有源区的整个宽度上延伸的第一导电类型的漏区; 所述第一导电类型的源极区域平行于所述栅极延伸并且在所述有源区域的极限之前至少在所述晶体管宽度的一侧上停止，所述间隔存在于所述源极区域的极限与所述有源区域的极限之间; 在栅极和所述间隔内延伸的第二导电类型的主体区域; 所述第二导电类型的更高掺杂区域在所述间隔的所述有效面积极限侧的一部分上延伸; 以及延伸穿过有效区域的整个宽度的细长源金属化。

    Image and depth pixel
    210.
    发明授权
    Image and depth pixel 有权

    公开(公告)号：US12040335B2

    公开(公告)日：2024-07-16

    申请号：US17944529

    申请日：2022-09-14

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Francois Roy

    IPC: H01L27/146 ,  H04N25/53 ,  H04N25/621 ,  H04N25/705 ,  H04N25/75 ,  H04N25/77

    CPC classification number: H01L27/14603 ,  H01L27/1463 ,  H04N25/53 ,  H04N25/621 ,  H04N25/705 ,  H04N25/75 ,  H04N25/77

    Abstract: A sensor includes pixels supported by a substrate doped with a first conductivity type. Each pixel includes a portion of the substrate delimited by a vertical insulation structure with an image sensing assembly and a depth sensing assembly. The image sensing assembly includes a first region of the substrate more heavily doped with the first conductivity type and a first vertical transfer gate completely laterally surrounding the first region. Each of the depth sensing assemblies includes a second region of the substrate more heavily doped with the first conductivity type a second vertical transfer gate opposite a corresponding portion of the first vertical transfer gate. The second region is arranged between the second vertical transfer gate and the corresponding portion of the first vertical transfer gate.

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