公开(公告)号：US10891413B1

公开(公告)日：2021-01-12

申请号：US16704762

申请日：2019-12-05

Applicant: Xilinx, Inc.

Inventor： Paul D. Kundarewich ,  Grigor S. Gasparyan ,  Mehrdad Eslami Dehkordi ,  Guenter Stenz

IPC: G06F30/333 ,  G06F30/392 ,  G06F30/327 ,  G06F111/04

Abstract: Disclosed approaches for processing a circuit design include providing access to checkpoint data of a design checkpoint of a circuit design and starting child processes by a parent process. An initial intermediate representation is generated by the parent process, and concurrent with the generating of the initial intermediate representation, the child processes load the checkpoint data into respective memory spaces. The parent process produces incremental updates to the design checkpoint. The parent process signals availability of the incremental updates to the child processes, which apply the incremental updates to the checkpoint data in the respective memory spaces. The child processes process the circuit design in response to completion of producing incremental updates by the parent placer process.

公开(公告)号：US10886906B1

公开(公告)日：2021-01-05

申请号：US15989623

申请日：2018-05-25

Applicant: Xilinx, Inc.

Inventor： Bob W. Verbruggen ,  Christophe Erdmann ,  Conrado K. Mesadri

IPC: H03K5/156 ,  G06F1/10

Abstract: A duty-cycle adjustment circuit receives a differential pair of input signals and generates an output signal based on the differential pair. The duty-cycle adjustment circuit drives the output signal to a logic-high state based on transitions of a first polarity in a first input signal of the differential pair, and drives the output signal to a logic-low state based on transitions of the first polarity in a second input signal of the differential pair. For example, rising-edge transitions of the output signal may be aligned with rising-edge transitions of the first input signal, and falling-edge transitions of the output signal may be aligned with rising-edge transitions of the second input signal. Alternatively, rising-edge transitions of the output signal may be aligned with falling-edge transitions of the first input signal, and falling-edge transitions of the output signal may be aligned with falling-edge transitions of the second input signal.

公开(公告)号：US10860765B1

公开(公告)日：2020-12-08

申请号：US16283552

申请日：2019-02-22

Applicant: Xilinx, Inc.

Inventor： Wuxi Li ,  Mehrdad Eslami Dehkordi ,  Xiaojian Yang

IPC: G06F17/50 ,  G06F30/34 ,  H03K19/17736 ,  G06F30/396

Abstract: Some examples described herein provide for clock tree generation for a programmable logic device, and more specifically, for clock tree generation in conjunction or simultaneous with placement of logic for a programmable logic device. In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to: generate clock trees in conjunction with placing logic for an application to be implemented in a programmable logic region of a programmable logic device; generate data routes between the placed logic; and generate a physical implementation of the application based on the placed logic, the clock trees, and the data routes. The physical implementation is capable of being loaded on the programmable logic region of the programmable logic device.

公开(公告)号：US10853308B1

公开(公告)日：2020-12-01

申请号：US16195218

申请日：2018-11-19

Applicant: Xilinx, Inc.

Inventor： Ramesh R. Subramanian ,  Ravinder Sharma ,  Jayaram Pvss ,  Michael Zapke ,  Manjunath Chepuri

IPC: G06F15/167 ,  G06F15/173 ,  G06F13/28

Abstract: A circuit for memory access includes a memory access control circuit. The memory access controller is coupled to a memory and configured to perform data transfers to retrieve data from the memory. The memory access control circuit includes a timing control circuit and a transfer control circuit. The timing control circuit is configured to determine first timing information based on a timing requirement for transmitting a first data stream to a first network; and determine a first fetch time for retrieving the first data stream from the memory based on the first timing information. The transfer control circuit is configured to retrieve the first data stream from the memory based on the first fetch time.

公开(公告)号：US20200371787A1

公开(公告)日：2020-11-26

申请号：US16421439

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Shail Aditya Gupta ,  Rishi Surendran

IPC: G06F9/30 ,  G06F9/46 ,  G06F9/50 ,  G06F8/41

Abstract: For an application having a software portion for implementation in a data processing engine (DPE) array of a device and a hardware portion for implementation in programmable logic (PL) of the device, an implementation flow is performed, using a processor executing a hardware compiler, on the hardware portion based on an interface block solution that maps logical resources used by the software portion to hardware of an interface block coupling the DPE array to the PL. In response to not meeting a design metric during the implementation flow, an interface block constraint is provided from the hardware compiler to a DPE compiler. In response to receiving the interface block constraint, an updated interface block solution is generated, using the processor executing the DPE compiler, and provided from the DPE compiler to the hardware compiler.

公开(公告)号：US10827044B2

公开(公告)日：2020-11-03

申请号：US16416587

申请日：2019-05-20

Applicant: XILINX, INC.

Inventor： Steve Pope ,  Kieran Mansley ,  Sian James ,  David J. Riddoch

IPC: H04L29/08 ,  H04L1/00 ,  H04L12/931

Abstract: Data is received at a buffer used by a protocol processing stack which protocol processes the received data. The received data is made available to, for example, an application, before the protocol processing of the data is complete. If the protocol processing is successful the data made available to the application is committed.

公开(公告)号：US10826492B2

公开(公告)日：2020-11-03

申请号：US16118899

申请日：2018-08-31

Applicant: Xilinx, Inc.

Inventor： Prashant Dubey ,  Sundeep Ram Gopal Agarwal

IPC: H01L25/065 ,  H03K17/687 ,  H01L27/06 ,  H01L23/48 ,  H01L23/528

Abstract: Examples of the present disclosure provide power gating for stacked die structures. In some examples, a stacked die structure comprises a first die and a second die bonded to the first die. In some examples, a power gated power path is from a bonding interface between the dies through TSVs in the second die, a power gating device in the second die, and routing of metallization layers in the second die to the circuit region in the second die. In some examples, a power gated power path comprises a power gating device in a power gating region of the first die and is configured to interrupt a flow of current through the power gated power path to a circuit region in the second die.

公开(公告)号：US10824584B1

公开(公告)日：2020-11-03

申请号：US15944295

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Sneha Bhalchandra Date ,  Jan Langer ,  Baris Ozgul ,  Goran H K Bilski

IPC: G06F9/24 ,  G06F15/177 ,  G06F15/173 ,  G06F15/80 ,  G06F9/4401

Abstract: A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

公开(公告)号：US10823780B1

公开(公告)日：2020-11-03

申请号：US16112433

申请日：2018-08-24

Applicant: Xilinx, Inc.

Inventor： Andrew Tabalujan ,  Xiaobao Wang ,  Gubo Huang

IPC: G01R31/28 ,  G01R19/257 ,  H04B17/20 ,  H01L25/065

Abstract: Examples herein describe techniques for testing a receiver interface on a die. In one embodiment, the die includes tester circuitry which includes a digital to analog convertor (DAC) which outputs an analog test signal to a selector circuit (e.g., a multiplexer) which forwards the analog test signal to a receiver. By varying the analog test signal, the tester circuitry can identify one or more trip points corresponding to the receiver. That is, by monitoring the output of the receiver, a testing application can determine when the output of the receiver switches states thereby indicating that the analog test signal at the input of the receiver corresponds to the trip point of the receiver. In this manner, internal circuitry (e.g., the tester circuitry) can be used to test a receiver interface that may otherwise be inaccessible.

公开(公告)号：US10819680B1

公开(公告)日：2020-10-27

申请号：US15915981

申请日：2018-03-08

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Umang Parekh ,  Jeffrey H. Seltzer ,  Khang K. Dao ,  Kyle Corbett

IPC: H04L29/06 ,  G06F13/42

Abstract: System and method generally relate to protection of a bussed network. In such a system, an access controller is configured for bussed communication via a communication bus to obtain a current transaction. An interface firewall is coupled for bussed communication with the access controller and configured to check for a fault associated with a transfer. A data processing device is coupled for communication with the interface firewall and configured to execute the current transaction to provide the transfer for the interface firewall. The interface firewall is configured to detect the fault associated with the transfer, to block access to the data processing device associated with the fault, and to communicate a blocked status for the data processing device.