公开(公告)号：US20190206718A1

公开(公告)日：2019-07-04

申请号：US15860121

申请日：2018-01-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas V. LiCausi ,  Shao Beng Law ,  Sunil K. Singh ,  Xunyuan Zhang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/02118 ,  H01L21/02274 ,  H01L21/31058 ,  H01L21/31111 ,  H01L21/76816 ,  H01L21/76828 ,  H01L23/528 ,  H01L23/53295 ,  H01L2221/1047

Abstract: Interconnect structures and methods for forming an interconnect structure. First and second metallization structures are formed in an intralayer dielectric layer. The intralayer dielectric layer is removed to form a cavity with an entrance between the first and second metallization structures. A dielectric layer is deposited on surfaces surrounding the cavity, over the first metallization structure, and over the second metallization structure. A sacrificial material is formed inside the cavity after the dielectric layer is deposited. A cap layer is deposited on the dielectric layer over the first metallization structure, the dielectric layer over the second metallization structure, and the sacrificial material inside the cavity to close the entrance to the cavity. After the cap layer is deposited, the sacrificial material is removed from the cavity. The dielectric layer and cap layer cooperate to encapsulate an air gap inside the cavity.

公开(公告)号：US10340146B2

公开(公告)日：2019-07-02

申请号：US15647495

申请日：2017-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rohit Galatage ,  Shariq Siddiqui ,  Chung-Ju Yang

IPC: H01L21/00 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L29/51

Abstract: Structures for reliability caps used in the manufacture of a field-effect transistor and methods for forming reliability caps used in the manufacture of a field-effect transistor. A layer comprised of a metal silicon nitride is deposited on a high-k dielectric material. The high-k dielectric material is thermally processed in an oxygen-containing ambient environment with the layer arranged as a cap between the high-k dielectric material and the ambient environment. Due at least in part to its composition, the layer blocks transport of oxygen from the ambient environment to the high-k dielectric material.

公开(公告)号：US10332897B2

公开(公告)日：2019-06-25

申请号：US16133176

申请日：2018-09-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaoqiang Zhang ,  Hui Zang ,  Ratheesh R. Thankalekshmi ,  Randy W. Mann

IPC: H01L27/11 ,  H01L29/66 ,  H01L27/02

Abstract: Various aspects include a static random access memory (SRAM) bitcell array structure. In some cases, the SRAM bitcell array structure includes at least one fin in an array of fins in a substrate, where a width of a first portion of the at least one fin is less than a width of a second portion of the at least one fin in the array of fins.

公开(公告)号：US10332834B2

公开(公告)日：2019-06-25

申请号：US15421698

申请日：2017-02-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu Wong ,  Jagar Singh ,  Ashish Baraskar ,  Min-hwa Chi

IPC: H01L29/06 ,  H01L23/525 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/283 ,  H01L27/112

Abstract: Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy.

公开(公告)号：US10332745B2

公开(公告)日：2019-06-25

申请号：US15597277

申请日：2017-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Sun ,  Ruilong Xie ,  Wenhui Wang ,  Yulu Chen ,  Erik Verduijn ,  Zhengqing John Qi ,  Guoxiang Ning ,  Daniel J. Dechene

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/768 ,  H01L21/3065

Abstract: Methods of forming printed patterns and structures formed using printed patterns. A first line and a second line are lithographically printed in a first layer composed of photoimageable material with a space arranged between the first line and the second line. A dummy assist feature is also lithographically printed in the photoimageable material of the first layer. A second layer underlying the first layer is etched with the first line, the second line, and the dummy assist feature present as an etch mask. The dummy assist feature is arranged on a portion of the space adjacent to the first line and supports the photoimageable material of the first line during etching.

公开(公告)号：US20190190453A1

公开(公告)日：2019-06-20

申请号：US15967172

申请日：2018-04-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： See Taur Lee ,  Abdellatif Bellaouar

IPC: H03F1/02 ,  H03F3/21 ,  H03F3/193 ,  H03F3/45 ,  H04B1/04

CPC classification number: H03F1/0205 ,  H03F3/193 ,  H03F3/21 ,  H03F3/45165 ,  H03F2200/451 ,  H03F2200/534 ,  H03F2200/541 ,  H04B1/04 ,  H04B2001/0408

Abstract: We disclose apparatus which may provide power amplification in millimeter-wave devices with reduced size and reduced power consumption, and methods of using such apparatus. One such apparatus comprises an input transformer; a first differential pair of injection transistors comprising a first transistor and a second transistor; a first back gate voltage source configured to provide a first back gate voltage to the first transistor; a second back gate voltage source configured to provide a second back gate voltage to the second transistor; a second differential pair of oscillator core transistors comprising a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are cross-coupled; a third back gate voltage source configured to provide a third back gate voltage to the third transistor; a fourth back gate voltage source configured to provide a fourth back gate voltage to the fourth transistor; and an output transformer.

公开(公告)号：US10325862B2

公开(公告)日：2019-06-18

申请号：US15657666

申请日：2017-07-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Andrew T. Kim ,  Ping-Chuan Wang

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

Abstract: Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

公开(公告)号：US10325819B1

公开(公告)日：2019-06-18

申请号：US15920303

申请日：2018-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Jessica Dechene ,  Huy Cao ,  Mitchell Rutkowski ,  Haigou Huang

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/768 ,  H01L21/306 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/3105

Abstract: At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. Subsequently, a replacement metal gate (RMG) process is performed in the gate region. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.

公开(公告)号：US10325811B2

公开(公告)日：2019-06-18

申请号：US15794600

申请日：2017-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David P. Brunco ,  Wei Zhao ,  Haiting Wang

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H01L21/762 ,  H01L27/088 ,  H01L21/8234

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. A plurality of sacrificial layers are formed on a dielectric layer. An opening is formed that includes a first section that extends through the sacrificial layers and a second section that extends through the dielectric layer. A semiconductor material is epitaxially grown inside the opening to form a fin. The first section of the opening has a first width dimension, and the second section of the opening has a second width dimension that is less than the first width dimension.

公开(公告)号：US10325808B2

公开(公告)日：2019-06-18

申请号：US15858691

申请日：2017-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ivan Huang ,  Elavarasan Pannerselvam ,  Vijay Sukumaran

IPC: H01L21/78 ,  H01L21/02 ,  H01L21/027 ,  H01L21/263 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/56 ,  H01L23/00

Abstract: A method of forming a 3D crack-stop structure in, through, and wrapped around the edges of a substrate to prevent through-substrate cracks from propagating and breaking the substrate and the resulting device are provided. Embodiments include providing a substrate including one or more dies; forming a continuous first trench near an outer edge of the substrate; forming a continuous second trench parallel to and on an opposite side of the first trench from the outer edge; forming a continuous row of vias parallel to and on an opposite side of the second trench from the first trench, forming a continuous third trench parallel to and near an outer edge of each of the dies; forming a protective layer wrapping around the outer edge of the substrate and over and filling the trenches and vias; and patterning active areas of the substrate between the vias and the third trench.