公开(公告)号：US09564372B2

公开(公告)日：2017-02-07

申请号：US14740987

申请日：2015-06-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc

Inventor： Balasubramanian Pranatharthiharan ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/82 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/417

CPC classification number: H01L21/823871 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823864 ,  H01L23/5226 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

Abstract: A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

Abstract translation: 制造双硅化物器件的方法包括：生长用于N型器件的源极和漏极（S / D）区域，在栅极结构上形成保护层，并且在N型器件的S / D区域上生长S / D区域用于P型设备。 第一电介质层被共形沉积，部分被去除以暴露S / D区域。 用于P型器件的暴露的S / D区域被硅化以形成衬垫。 第二电介质层被共形沉积。 在第二电介质层上形成电介质填充物。 接触孔通过第二介电层打开，露出P型器件的衬垫，露出N型器件的保护层。 通过打开保护层来暴露N型器件的S / D区域。 暴露的与栅极结构相邻的S / D区域被硅化以形成用于N型器件的衬垫。 触点形成。

公开(公告)号：US20170033196A1

公开(公告)日：2017-02-02

申请号：US15282836

申请日：2016-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Andrew M. Greene ,  Ryan O. Jung ,  Ruilong Xie ,  Peng Xu

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/027

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/60 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78

Abstract: A method for forming a gate cut region includes forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate, forming a dummy gate dielectric and a dummy gate conductor in the trench and planarizing a top surface to reach the hard mask. The dummy gate conductor is patterned to form a cut trench in a cut region. The dummy gate conductor is recessed, and the cut trench is filled with a first dielectric material. The dummy layer is removed and spacers are formed. A gate line is opened up and the dummy gate conductor is removed from the gate line trench. A gate dielectric and conductor are deposited, and a gate cap layer provides a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure.

Abstract translation: 一种用于形成栅极切割区域的方法包括通过形成在衬底上的硬掩模，虚设层和虚设电介质形成锥形轮廓栅极线沟槽，在沟槽中形成虚拟栅极电介质和虚拟栅极导体并平面化顶部 表面达到硬面膜。 虚拟栅极导体被图案化以在切割区域中形成切割沟槽。 虚拟栅极导体是凹进的，并且切割沟槽填充有第一介电材料。 去除虚设层并形成间隔物。 栅极线被打开，并且虚拟栅极导体从栅极线沟槽移除。 沉积栅介质和导体，并且栅极盖层提供耦合到切割沟槽中的第一电介质材料以形成切割最后结构的第二电介质。

公开(公告)号：US09559009B2

公开(公告)日：2017-01-31

申请号：US14876212

申请日：2015-10-06

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Theodorus E. Standaert ,  Ruilong Xie

IPC: H01L21/311 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/088 ,  H01L29/08 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L21/823437 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785

Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

Abstract translation: 形成跨越多个半导体材料部分的栅极结构。 源极区域和漏极区域形成在多个半导体材料部分中，并且形成横向围绕栅极结构的栅极间隔物。 通过选择性外延工艺从源极和漏极区域形成外延有源区。 通过切割掩模和蚀刻将栅极结构和栅极间隔物的组装切成多个部分以形成多个栅极组件。 每个门组件包括栅极结构部分和由栅极结构部分横向隔开的两个分离的栅极间隔部分。 可以从栅极间隔物的侧壁的周围去除外延有源区的一部分，以防止外延有源区中的电短路。 可以使用电介质间隔物或电介质衬垫来限制形成金属半导体合金的区域。

公开(公告)号：US09553028B2

公开(公告)日：2017-01-24

申请号：US14219365

申请日：2014-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Ryan Ryoung-Han Kim

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L23/485 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/823475 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/088 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a layer of insulating material above first and second transistors, within the layer of insulating material, forming a set of initial device-level contacts for each of the first and second transistors, wherein each set of initial device-level contacts comprises a plurality of source/drain contacts and a gate contact, forming an initial local interconnect structure that is conductively coupled to one of the initial device-level contacts in each of the first and second transistors, and removing the initial local interconnect structure and portions, but not all, of the initial device-level contacts for each the first and second transistors. The method also includes forming a copper local interconnect structure and copper caps above the recessed device-level contacts.

Abstract translation: 一种方法包括在绝缘材料层内的第一和第二晶体管之上形成绝缘材料层，形成用于第一和第二晶体管中的每一个的一组初始器件级触点，其中每组初始器件级触点包括 多个源极/漏极触点和栅极接触，形成初始局部互连结构，其导电耦合到第一和第二晶体管中的每一个中的初始器件级触点之一，以及去除初始局部互连结构和部分， 但不是所有的第一和第二晶体管的初始器件级触点。 该方法还包括在凹入的器件级触点上方形成铜局部互连结构和铜帽。

公开(公告)号：US09536877B2

公开(公告)日：2017-01-03

申请号：US14195484

申请日：2014-03-03

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L27/088 ,  H01L23/485 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L27/088 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One example disclosed herein involves forming source/drain conductive contacts to first and second source/drain regions, the first source/drain region being positioned between a first pair of transistor devices having a first gate pitch dimension, the second source/drain region being positioned between a second pair of transistor devices having a second gate pitch dimension that is greater than the first gate pitch dimension, wherein the first and second pairs of transistor devices have a gate structure and sidewall spacers positioned adjacent the gate structure.

Abstract translation: 本文公开的一个示例涉及将源极/漏极导电触点形成到第一和第二源极/漏极区域，第一源极/漏极区域位于具有第一栅极间距尺​​寸的第一对晶体管器件之间，第二源极/漏极区域被定位 在具有大于第一栅极间距尺​​寸的第二栅极间距尺​​寸的第二对晶体管器件之间，其中第一和第二对晶体管器件具有栅极结构和邻近栅极结构定位的侧壁间隔物。

公开(公告)号：US20160351411A1

公开(公告)日：2016-12-01

申请号：US14726712

申请日：2015-06-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Catherine B. Labelle

IPC: H01L21/306 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/3083

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin-removal masking layer comprised of a plurality of line-type features, each of which is positioned above one of the fins, and a masking material positioned at least between adjacent features of the fin-removal masking layer and above portions of an insulating material in the trenches between the fins. The method also includes performing an anisotropic etching process through the fin-removal masking layer to remove the portions of the fins to be removed.

Abstract translation: 本文公开的一种说明性方法除其他外包括形成由多个线型特征组成的鳍去除掩模层，每个线型特征位于其中一个翅片上方，并且掩蔽材料至少位于相邻特征之间 翅片去除掩模层和鳍片之间的沟槽中的绝缘材料的上述部分。 该方法还包括通过散热器去除掩模层进行各向异性蚀刻工艺，以除去待除去的散热片的部分。

公开(公告)号：US09472670B1

公开(公告)日：2016-10-18

申请号：US15085376

申请日：2016-03-30

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Rama Kambhampati ,  Junli Wang ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material.

Abstract translation: 一种用于形成场效应晶体管的方法包括在第一鳍上形成第一虚拟栅极堆叠，在第二鳍片上形成第二虚拟栅极叠层，在第一伪栅极叠层上沉积第一层间隔物材料， 虚拟栅极堆叠和第二鳍片，在第一伪栅极堆叠和第一鳍片上构图第一掩模层，蚀刻以去除第一层间隔物材料的部分并形成邻近第二伪栅极叠层的间隔区， 第一掩模层，在所述第二鳍上外延生长硅材料，在所述第一隔离层材料层上沉积氧化物层，所述第一外延材料和所述第二伪栅极堆叠，以及在所述层上沉积第二隔离层材料层 的氧化物质。

公开(公告)号：US09472446B2

公开(公告)日：2016-10-18

申请号：US14307902

申请日：2014-06-18

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/336 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/76224 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/1029 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853

Abstract: One method disclosed includes, among other things, forming an overall fin structure having a stepped cross-sectional profile, the fin structure having an upper part and a lower part positioned under the upper part, wherein the upper part has a first width and the lower part has a second width that is less than the first width, forming a layer of insulating material in trenches adjacent the overall fin structure such that the upper part of the overall fin structure and a portion of the lower part of the overall fin structure are exposed above an upper surface of the layer of insulating material, and forming a gate structure around the exposed upper part of the overall fin structure and the exposed portion of the lower part of the overall fin structure.

Abstract translation: 所公开的一种方法包括形成具有阶梯状横截面轮廓的整体翅片结构，翅片结构具有位于上部下方的上部和下部，其中上部具有第一宽度和下部 部分具有小于第一宽度的第二宽度，在邻近整个翅片结构的沟槽中形成绝缘材料层，使得整个翅片结构的上部和整个翅片结构的下部的一部分暴露 在绝缘材料层的上表面之上，并且围绕整个翅片结构的暴露的上部和整个翅片结构的下部的暴露部分形成栅极结构。

公开(公告)号：US20160293757A1

公开(公告)日：2016-10-06

申请号：US14931409

申请日：2015-11-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andreas Knorr

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L29/7827 ,  H01L21/823431 ,  H01L21/823487 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L2029/7858

Abstract: One example of a novel integrated circuit product disclosed herein includes, among other things, a lateral FinFET device comprising a first gate structure having a first upper surface positioned above a semiconductor substrate and a vertical FinFET device comprising a second gate structure having a second upper surface positioned above the semiconductor substrate, wherein the first upper surface of the first gate structure is positioned at a first height level above a reference surface of the semiconductor substrate and the second upper surface of the second gate structure is positioned at a second height level above the reference surface of the semiconductor substrate, the first height level being greater than the second height level.

Abstract translation: 本文公开的新颖的集成电路产品的一个示例尤其包括横向FinFET器件，其包括具有位于半导体衬底上方的第一上表面的第一栅极结构和包括具有第二上表面的第二栅极结构的垂直FinFET器件 位于所述半导体衬底上方，其中所述第一栅极结构的所述第一上表面位于所述半导体衬底的参考表面上方的第一高度水平处，并且所述第二栅极结构的所述第二上表面位于所述第二栅极结构的第二高度水平 半导体衬底的参考表面，第一高度水平大于第二高度水平。

公开(公告)号：US09461171B2

公开(公告)日：2016-10-04

申请号：US14283636

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hoon Kim ,  Naim Moumen ,  Chanro Park ,  William J. Taylor, Jr.

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L21/768 ,  H01L21/285 ,  H01L23/485 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76805 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, performing an epitaxial deposition process to form an epi semiconductor material on the active region in the source/drain region of the device, performing an etching process on the epi semiconductor material to remove a portion of the epi semiconductor material so as to define at least one epi recess in the epi semiconductor material, forming a metal silicide layer on the upper surface of the epi semiconductor material and in the at least one epi recess in the epi semiconductor material, and forming a conductive structure that is conductively coupled to the metal silicide layer.

Abstract translation: 所公开的一种方法包括在半导体衬底的有源区上方形成栅极结构，执行外延沉积工艺以在器件的源极/漏极区域中的有源区上形成外延半导体材料，进行蚀刻 处理外延半导体材料以去除外延半导体材料的一部分，以便限定外延半导体材料中的至少一个外延凹部，在外延半导体材料的上表面上形成金属硅化物层，并且在至少一个 epi凹槽，并且形成导电耦合到金属硅化物层的导电结构。