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    PREVENTION OF FIN EROSION FOR SEMICONDUCTOR DEVICES
    221.
    发明申请
    PREVENTION OF FIN EROSION FOR SEMICONDUCTOR DEVICES 有权
    防止半导体器件的腐蚀

    公开(公告)号：US20140124840A1

    公开(公告)日：2014-05-08

    申请号：US13670674

    申请日：2012-11-07

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

    Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/311

    CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

    Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。

    Methods of removing dummy fin structures when forming finFET devices
    222.
    发明授权
    Methods of removing dummy fin structures when forming finFET devices 有权
    在形成finFET器件时去除虚拟鳍片结构的方法

    公开(公告)号：US08703557B1

    公开(公告)日：2014-04-22

    申请号：US13863044

    申请日：2013-04-15

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC: H01L21/84 ,  H01L21/00

    CPC classification number: H01L29/6681 ,  H01L21/823821

    Abstract: One method disclosed herein includes forming a plurality of fin-formation trenches in a substrate that defines a plurality of fins, wherein at least one of the fins is a dummy fin, forming an insulating material that fills at least a portion of the trenches, forming a recess in a masking layer formed above the insulating material, forming a sidewall spacer on sidewalls of the recess so as to define a spacer opening, performing at least one first etching process on the masking layer through the spacer opening to define an opening in the masking layer that exposes a portion of the insulating material and the dummy fin, and performing at least one second etching process to remove at least a portion of the dummy fin and thereby define an opening in the insulating material.

    Abstract translation: 本文公开的一种方法包括在限定多个翅片的基底中形成多个翅片形成沟槽，其中至少一个翅片是虚拟翅片，形成填充沟槽的至少一部分的绝缘材料，形成 在绝缘材料上形成的掩模层中的凹槽，在凹槽的侧壁上形成侧壁间隔物，以限定间隔开口，通过间隔开口在掩模层上执行至少一个第一蚀刻工艺，以在 暴露绝缘材料和虚拟鳍片的一部分的掩模层，并且执行至少一个第二蚀刻工艺以去除所述虚拟鳍片的至少一部分，从而限定所述绝缘材料中的开口。

    SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS AND LOW-K SPACERS
    223.
    发明申请
    SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS AND LOW-K SPACERS 有权
    具有自对准接触和低K间隔的半导体器件

    公开(公告)号：US20140042502A1

    公开(公告)日：2014-02-13

    申请号：US13957587

    申请日：2013-08-02

    Applicant: Globalfoundries Inc.

    Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC: H01L29/78

    CPC classification number: H01L29/78 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

    Abstract: One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.

    Abstract translation: 本文公开的一种说明性方法包括去除牺牲侧壁间隔物的一部分，从而暴露牺牲栅电极的侧壁的至少一部分，并在牺牲栅电极的暴露的侧壁上形成衬垫层。 在该示例中，该方法还包括在衬垫层之上形成牺牲间隙填充材料，暴露和去除牺牲栅极电极，从而限定由衬里层横向限定的栅极腔，形成替代栅极结构，去除牺牲层 间隙填充材料并形成邻近衬层的低k侧壁间隔物。 还公开了一种器件，其包括栅极覆盖层，位于栅极绝缘层的两个直立部分中的每一个上的氮化硅或氮氧化硅层，以及位于氮化硅或氮氧化硅层上的低k侧壁间隔物。

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