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    Techniques for parallel data decompression
    243.
    发明授权
    Techniques for parallel data decompression 有权

    公开(公告)号：US10230392B2

    公开(公告)日：2019-03-12

    申请号：US15393190

    申请日：2016-12-28

    Applicant: INTEL CORPORATION

    Inventor： Vinodh Gopal ,  James D. Guilford

    IPC: H03M7/00 ,  H03M7/40 ,  H03M7/30

    Abstract: Techniques and apparatus for parallel decompression are described. In one embodiment, for example, an apparatus to provide parallel decompression may include at least one memory and logic for a decompression component, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine decompression information of a compressed data unit, annotate the compressed data unit with at least a portion of the decompression information to generate an annotated data unit, parallel-decode the annotated data unit to generate a plurality of intermediate elements, and decode and merge the plurality of intermediate elements to generate a decompressed data unit. Other embodiments are described and claimed.

    Techniques for data compression verification
    244.
    发明授权
    Techniques for data compression verification 有权

    公开(公告)号：US10224959B2

    公开(公告)日：2019-03-05

    申请号：US15935117

    申请日：2018-03-26

    Applicant: INTEL CORPORATION

    Inventor： Vinodh Gopal ,  James D. Guilford ,  Kirk S. Yap ,  Daniel F. Cutter ,  Wajdi K. Feghali

    IPC: H03M7/40 ,  H03M7/30 ,  H04L1/24

    Abstract: Techniques and apparatus for verification of compressed data are described. In one embodiment, for example an apparatus to provide verification of compressed data may include at least one memory and logic, at least a portion of comprised in hardware coupled to the at least one memory, the logic to access compressed data, access compression information associated with the compressed data, decompress at least a portion of the compressed data to generate decompressed data, and verify the compressed data via a comparison of the decompressed data with the compression information. Other embodiments are described and claimed.

    Key-value deduplication
    245.
    发明授权
    Key-value deduplication 有权

    公开(公告)号：US10216445B2

    公开(公告)日：2019-02-26

    申请号：US15639450

    申请日：2017-06-30

    Applicant: Intel Corporation

    Inventor： Peng Li ,  Jawad B. Khan ,  Sanjeev N. Trika ,  Vinodh Gopal

    IPC: G06F3/06

    Abstract: One embodiment provides an apparatus. The apparatus include a device storage logic. The device storage logic is to determine a key-based pointer based, at least in part, on a key included in an input key-value (KV) pair received from a host device and to determine whether a unique input KV data block included in the input KV pair is duplicated in a nonvolatile memory circuitry of a storage device. The device storage logic is further to set a descriptor pointer associated with the unique input KV data block to point to a physical nonvolatile memory (NVM) address associated with an existing unique data block and increment a first reference count associated with the existing unique data block, if the unique input KV data block is a duplicate of the existing unique data block, or store the input KV data block to a physical NVM location associated with a selected physical NVM address, set the descriptor pointer to point to the selected physical NVM address and set a second reference count associated with the selected physical NVM address to one, if the unique input KV data block is not duplicated in the NVM circuitry.

    TECHNOLOGIES FOR STRUCTURED DATABASE QUERY FOR FINDING UNIQUE ELEMENT VALUES
    246.
    发明申请
    TECHNOLOGIES FOR STRUCTURED DATABASE QUERY FOR FINDING UNIQUE ELEMENT VALUES 审中-公开

    公开(公告)号：US20190042611A1

    公开(公告)日：2019-02-07

    申请号：US15868594

    申请日：2018-01-11

    Applicant: Intel Corporation

    Inventor： Kirk Yap ,  James Guilford ,  Daniel Cutter ,  Vinodh Gopal

    IPC: G06F17/30

    Abstract: Technologies for determining unique values include a computing device that further includes one or more accelerator devices. Each accelerator device is to receive input data and query configuration data, the input data including a packed array of unsigned integers of column data from a database and the query configuration data including an element width of the input data, and generate, in response to receiving the query configuration data, a bit-map output table based on the query configuration data, generate a write request for each element of the input data to set a corresponding bit-map output bit of the bit-map output table which corresponds to an element value of the corresponding element. Subsequently, the accelerator device is further to set the corresponding bit-map output bit to indicate a presence of the corresponding element and output the bit-map output table indicative of unique elements that are present in the input data.

    Hardware accelerators and methods for stateful compression and decompression operations
    249.
    发明授权
    Hardware accelerators and methods for stateful compression and decompression operations 有权

    公开(公告)号：US10169073B2

    公开(公告)日：2019-01-01

    申请号：US14975847

    申请日：2015-12-20

    Applicant: Intel Corporation

    Inventor： Tracy G. Drysdale ,  James D. Guilford ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  James T. Kukunas

    IPC: G06F9/46 ,  G06F9/50

    Abstract: Methods and apparatuses relating to stateful compression and decompression operations are described. In one embodiment, hardware processor includes a core to execute a thread and offload at least one of a compression and decompression thread, and a hardware compression and decompression accelerator to execute the at least one of the compression and decompression thread to consume input and generate output data, wherein the hardware compression and decompression accelerator is coupled to a plurality of input buffers to store the input data, a plurality of output buffers to store the output data, an input buffer descriptor array with an entry for each respective input buffer, an input buffer response descriptor array with a corresponding response entry for each respective input buffer, an output buffer descriptor array with an entry for each respective output buffer, and an output buffer response descriptor array with a corresponding response entry for each respective output buffer.

    Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality
    250.
    发明授权
    Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality 有权

    公开(公告)号：US10158484B2

    公开(公告)日：2018-12-18

    申请号：US15289819

    申请日：2016-10-10

    Applicant: Intel Corporation

    Inventor： Sean M. Gulley ,  Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

    IPC: H04L9/08 ,  H04L9/06 ,  G06F21/72 ,  G09C1/00 ,  G06F9/30 ,  G06F9/38

    Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

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