中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

49 records (took 0.025 seconds)

    Method and apparatus for accelerated data compression with hints and filtering
    3.
    发明授权
    Method and apparatus for accelerated data compression with hints and filtering 有权

    公开(公告)号：US09917597B1

    公开(公告)日：2018-03-13

    申请号：US15382031

    申请日：2016-12-16

    Applicant: Intel Corporation

    Inventor： Daniel F. Cutter ,  Vinodh Gopal ,  James D. Guilford

    IPC: H03M7/30 ,  H04L29/06

    CPC classification number: H03M7/3086 ,  H03M7/30 ,  H03M7/6029

    Abstract: A processor includes a decoder to decode an instruction to compress an input data stream and an execution unit for executing the instruction. The execution unit to generate metadata for a current input of the input data stream, the metadata comprises a first hint based on a portion of a current input that represents the input data stream at a current offset, select a first pointer to identify a location in a history buffer in a hash chain, determine whether the metadata generated for the current input matches metadata previously generated for the first pointer, and filter the first pointer from a search for a best match for the current input in the history buffer based on the determination that at least a portion of the metadata for the current input does not match a portion of the metadata for the first pointer.

    HETEROGENEOUS COMPRESSION ARCHITECTURE FOR OPTIMIZED COMPRESSION RATIO
    5.
    发明申请
    HETEROGENEOUS COMPRESSION ARCHITECTURE FOR OPTIMIZED COMPRESSION RATIO 有权

    公开(公告)号：US20170111059A1

    公开(公告)日：2017-04-20

    申请号：US15393599

    申请日：2016-12-29

    Applicant: Intel Corporation

    Inventor： James D. Guilford ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel F. Cutter

    IPC: H03M7/40 ,  H03M7/30

    CPC classification number: H03M7/40 ,  H03M7/30 ,  H03M7/3086

    Abstract: A processing device includes an accelerator circuit to identify a byte in a byte stream, determine whether a first byte string starting from a first byte position of the byte matches a second byte string starting from a second byte position, responsive to determining that the first byte string matches the second byte string, generate a token comprising a first symbol encoding a length of the first byte string and a second symbol encoding a byte distance between the first byte position and the second byte position, and responsive to determining that the first byte string does not match another byte string, generate the token comprising the first symbol comprising the byte and a second symbol encoding a determined value.

    Heterogeneous compression architecture for optimized compression ratio
    7.
    发明授权
    Heterogeneous compression architecture for optimized compression ratio 有权
    用于优化压缩比的异构压缩架构

    公开(公告)号：US09537504B1

    公开(公告)日：2017-01-03

    申请号：US14866115

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： James D. Guilford ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel F. Cutter

    IPC: H03M7/30 ,  H03M7/40

    CPC classification number: H03M7/40 ,  H03M7/30 ,  H03M7/3086

    Abstract: A processing device includes a storage device to store data and a processor, operably coupled to the storage device, the processor to receive a token stream comprising a plurality of tokens generated based on a byte stream comprising a plurality of bytes, wherein each token in the token stream comprises at least one symbol associated with a respective byte in the byte stream, and wherein the at least one symbol represents one of the respective byte, a length of a first byte string starting from the respective byte, or a byte distance between the first byte string and a matching second byte string, generate a graph comprising a plurality of nodes and edges based on the token stream, wherein each token in the token stream is associated with a respective node connected by at least one edge to another node, and wherein the at least one edge is associated with a cost function to encode the at least one symbol stored in the each token, identify, based on the graph, a path between a first node associated with a beginning token of the token stream and an end node associated with a last token of the token stream, wherein the path comprises a subset of nodes and edges linking the subset of nodes, and perform variable-length encoding of a subset of tokens associated with the subset of nodes to generate an output data.

    Abstract translation: 处理设备包括存储数据的存储设备和可操作地耦合到存储设备的处理器，处理器接收包括基于包括多个字节的字节流生成的多个令牌的令牌流，其中， 标记流包括与字节流中的相应字节相关联的至少一个符号，并且其中至少一个符号表示相应字节中的一个，从相应字节开始的第一字节串的长度，或 第一字节串和匹配的第二字节串，基于令牌流生成包括多个节点和边的图形，其中令牌流中的每个令牌与由至少一个边缘连接到另一个节点的相应节点相关联，以及 其中所述至少一个边缘与成本函数相关联，以对存储在每个令牌中的所述至少一个符号进行编码，基于所述图表来识别第一点之间的路径 e与令牌流的开始令牌和与令牌流的最后一个令牌相关联的结束节点相关联，其中该路径包括链接节点子集的节点和边缘的子集，并且执行子集的子集的可变长度编码 与节点子集相关联的令牌以生成输出数据。

    Method and apparatus for hybrid compression processing for high levels of compression
    9.
    发明授权
    Method and apparatus for hybrid compression processing for high levels of compression 有权

    公开(公告)号：US10224956B2

    公开(公告)日：2019-03-05

    申请号：US15816959

    申请日：2017-11-17

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  James D. Guilford ,  Daniel F. Cutter

    IPC: G06F3/06 ,  H03M7/30

    Abstract: In one embodiment, an apparatus comprises a first compression engine to receive a first compressed data block from a second compression engine that is to generate the first compressed data block by compressing a first plurality of repeated instances of data that each have a length greater than or equal to a first length. The first compression engine is further to compress a second plurality of repeated instances of data of the first compressed data block that each have a length greater than or equal to a second length, the second length being shorter than the first length, wherein each compressed repeated instance of the first and second pluralities of repeated instances comprises a location and length of a data instance that is repeated. The apparatus further comprises a memory buffer to store the compressed first and second plurality of repeated instances of data.

    Technologies for efficiently compressing data with run detection
    10.
    发明授权
    Technologies for efficiently compressing data with run detection 有权

    公开(公告)号：US10033404B2

    公开(公告)日：2018-07-24

    申请号：US15639289

    申请日：2017-06-30

    Applicant: Intel Corporation

    Inventor： Daniel F. Cutter ,  Vinodh Gopal ,  James D. Guilford

    IPC: H03M7/38 ,  H03M7/30

    Abstract: Technologies for efficiently compressing data with run detection include a compute device. The compute device is to produce a hash as a function of a symbol at a present position and a predefined number of symbols after the present position in an input stream, determine whether the symbol at the present position is part of a run, obtain, from a hash table, a chain of pointers to previous positions in the input stream associated with the hash, determine, as a function of whether the symbol is part of a run and to identify a matched string, a number of strings referenced by the chain of pointers to compare to a string associated with the present position in the input stream, and output, in response to an identification of a matched string, a reference to the matched string in a set of compressed output data.

Patent Agency Ranking