公开(公告)号：US09660022B2

公开(公告)日：2017-05-23

申请号：US14830756

申请日：2015-08-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Chia-Hsun Tseng

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method of fabricating a single diffusion break includes providing a fin with two gate structures crossing the fin and a middle dummy gate structure crossing the fin, wherein the middle dummy gate structure is sandwiched by the gate structures. Later, numerous spacers are formed and each spacer respectively surrounds the gate structures and the middle dummy gate structure. Then, the middle dummy gate structure, and part of the fin directly under the middle dummy gate structure are removed to form a recess. Finally, an isolating layer in the recess is formed to close an entrance of the recess so as to form a void embedded within the recess.

公开(公告)号：US20170125552A1

公开(公告)日：2017-05-04

申请号：US15403187

申请日：2017-01-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung ,  En-Chiuan Liou

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/225 ,  H01L21/306

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/18 ,  H01L21/2255 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7834 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a fin-shaped structure thereon and the fin-shaped structure includes a top portion and a bottom portion; forming a gate structure on the fin-shaped structure; forming a cap layer on the top portion of the fin-shaped structure not covered by the gate structure; performing an annealing process to drive germanium from the cap layer to the top portion of the fin-shaped structure; removing the cap layer; and forming an epitaxial layer around the top portion of the fin-shaped structure.

公开(公告)号：US09607892B2

公开(公告)日：2017-03-28

申请号：US15201511

申请日：2016-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Chih-Sen Huang ,  Yu-Cheng Tung

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/66 ,  H01L21/308 ,  H01L23/522 ,  H01L23/485 ,  H01L29/66 ,  H01L29/00

CPC classification number: H01L21/76895 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/3085 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/00 ,  H01L29/66545 ,  H01L29/66553

Abstract: A method for fabricating semiconductor device comprising: providing a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; removing part of the gate structure; forming a first mask layer on the first ILD layer and the gate structure; removing the first mask layer on the first ILD layer and part of the first mask layer on the gate structure for forming a first hard mask on the gate structure; forming a second mask layer on the first ILD layer, the first hard mask, and the gate structure; and planarizing the second mask layer to form a second hard mask on the gate structure, in which the top surfaces of the first hard mask, the second hard mask, and the first ILD layer are coplanar.

公开(公告)号：US20170062618A1

公开(公告)日：2017-03-02

申请号：US14873617

申请日：2015-10-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/42384 ,  H01L29/66969 ,  H01L2029/42388

Abstract: A semiconductor device is provided, comprising a substrate with a first insulating film formed thereon, and a transistor formed on the first insulating film. The transistor at least comprises an oxide semiconductor layer formed on the first insulating film, a first gate insulation film formed on the oxide semiconductor layer, a gate electrode formed above the first gate insulation film, and spacers formed on the oxide semiconductor layer. The spacers at least cover the sidewalls of the first gate insulation film and the sidewalls of the gate electrode. The gate electrode has a gate width and the first gate insulation film has a first width, wherein the gate width is different from the first width.

Abstract translation: 提供一种半导体器件，包括其上形成有第一绝缘膜的衬底和形成在第一绝缘膜上的晶体管。 晶体管至少包括形成在第一绝缘膜上的氧化物半导体层，形成在氧化物半导体层上的第一栅极绝缘膜，形成在第一栅极绝缘膜上方的栅电极和形成在氧化物半导体层上的间隔物。 间隔件至少覆盖第一栅绝缘膜的侧壁和栅电极的侧壁。 栅电极具有栅极宽度，第一栅极绝缘膜具有第一宽度，其中栅极宽度与第一宽度不同。

公开(公告)号：US09570339B2

公开(公告)日：2017-02-14

申请号：US14687932

申请日：2015-04-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/70 ,  H01L21/762 ,  H01L21/033 ,  H01L29/06 ,  H01L29/34 ,  H01L21/8234

CPC classification number: H01L21/76229 ,  H01L21/033 ,  H01L21/3086 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/34

Abstract: A semiconductor process including the following step is provided. A sacrificial layer is formed in a substrate. The sacrificial layer and the substrate are etched to form a trench in the sacrificial layer and the substrate. A first isolation material fills the trench, thereby a first isolation structure being formed. The sacrificial layer is patterned to form a plurality of sacrificial patterns. A plurality of spacers are formed beside the sacrificial patterns respectively. The sacrificial patterns are removed. Layouts of the spacers are transferred into the substrate, so that a plurality of fin structures are formed in the substrate. The spacers are then removed. The present invention also provides a semiconductor structure formed by said semiconductor process.

Abstract translation: 提供包括以下步骤的半导体工艺。 在衬底中形成牺牲层。 蚀刻牺牲层和衬底以在牺牲层和衬底中形成沟槽。 第一隔离材料填充沟槽，从而形成第一隔离结构。 将牺牲层图案化以形成多个牺牲图案。 在牺牲图案旁边分别形成多个间隔物。 牺牲图案被去除。 间隔物的布置被转移到基底中，使得在基底中形成多个翅片结构。 然后移除间隔物。 本发明还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US20170040415A1

公开(公告)日：2017-02-09

申请号：US14840038

申请日：2015-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Chun-Yuan Wu

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/283 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/76232 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有第一区域和第二区域的衬底; 在所述第一区域和所述第二区域上的所述鳍状结构周围形成多个鳍状结构和第一浅沟槽隔离（STI）; 在所述第二区域上形成图案化的硬掩模; 从所述第一区域去除所述鳍状结构和所述第一STI; 在所述第一区域上形成第二STI; 去除图案化的硬掩模; 以及在第二STI上形成栅极结构。

公开(公告)号：US20160365452A1

公开(公告)日：2016-12-15

申请号：US14793721

申请日：2015-07-07

Applicant: United Microelectronics Corp.

Inventor： Yu-Cheng Tung ,  En-Chiuan Liou

IPC: H01L29/78 ,  H01L21/324 ,  H01L29/06 ,  H01L21/306 ,  H01L21/02 ,  H01L29/66 ,  H01L29/167

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/18 ,  H01L21/2255 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7834 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a fin-shaped structure thereon and the fin-shaped structure includes a top portion and a bottom portion; forming a gate structure on the fin-shaped structure; forming a cap layer on the top portion of the fin-shaped structure not covered by the gate structure; performing an annealing process to drive germanium from the cap layer to the top portion of the fin-shaped structure; removing the cap layer; and forming an epitaxial layer around the top portion of the fin-shaped structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上至少具有鳍状结构的基底，并且所述鳍状结构包括顶部和底部; 在鳍状结构上形成栅极结构; 在未被栅极结构覆盖的鳍状结构的顶部上形成盖层; 执行退火处理以将锗从盖层驱动到鳍状结构的顶部; 去除盖层; 以及围绕所述鳍状结构的顶部部分形成外延层。

公开(公告)号：US20160299433A1

公开(公告)日：2016-10-13

申请号：US14714357

申请日：2015-05-18

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: G03F7/20 ,  G03F7/36

CPC classification number: G03F7/203 ,  G03F7/2002 ,  G03F7/70091 ,  G03F7/70125 ,  G03F7/7025

Abstract: An illumination system includes a light source used to generate a light and an opaque plate. The opaque plate is disposed between the light source and a photomask and includes an annular aperture and an aperture dipole. The annular aperture has an inner side and an outer side. The aperture dipole includes at least one first aperture and at least one second aperture. The first aperture and the second aperture connected to the annular aperture respectively and protruding out from the outer side of the annular aperture are disposed symmetrically with respect to a center of the annular aperture.

Abstract translation: 照明系统包括用于产生光和不透明板的光源。 不透明板设置在光源和光掩模之间，并且包括环形孔和孔偶极子。 环形孔具有内侧和外侧。 孔径偶极子包括至少一个第一孔径和至少一个第二孔径。 分别连接到环形孔并从环形孔的外侧突出的第一孔和第二孔相对于环形孔的中心对称设置。

公开(公告)号：US20160132626A1

公开(公告)日：2016-05-12

申请号：US14534190

申请日：2014-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: G06F17/50

CPC classification number: G03F7/70466 ,  G03F1/70

Abstract: A method of decomposing layout design for preparing a photomask set printed onto a wafer by photolithography includes the following steps. An integrated circuit layout design including several features is obtained. The overlay relation of these features is recognized to classify these features into a first group and a second group. These features printed onto different layers of the wafer are distinguished to decompose the first group into a first feature and a third feature, and the second group into a second feature and a fourth feature. The first feature is outputted to a first photomask, the second feature is outputted to a second photomask, a third feature is outputted to a third photomask and a fourth feature is outputted to a fourth photomask. A method of forming a photomask set and a method of fabricating an integrated circuit are also provided.

Abstract translation: 通过光刻法分解印刷在晶片上的光掩模组的布局设计分解方法包括以下步骤。 获得包括几个特征的集成电路布局设计。 识别这些特征的覆盖关系将这些特征分类成第一组和第二组。 印刷在晶片的不同层上的这些特征被区分为将第一组分解成第一特征和第三特征，而将第二组分解为第二特征和第四特征。 将第一特征输出到第一光掩模，将第二特征输出到第二光掩模，将第三特征输出到第三光掩模，将第四特征输出到第四光掩模。 还提供了形成光掩模组的方法和制造集成电路的方法。

公开(公告)号：US20160104673A1

公开(公告)日：2016-04-14

申请号：US14510119

申请日：2014-10-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L23/522 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L23/532

CPC classification number: H01L29/66795 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/785

Abstract: A FinFET includes a fin-shaped structure, a gate structure, an epitaxial layer, an interlayer dielectric layer, an opening, a germanium cap and a contact plug. The fin-shaped structure is disposed on the substrate. The gate structure covers a portion of the fin-shaped structure. The epitaxial layer is disposed on the fin-shaped structure adjacent to the gate structure. The interlayer dielectric layer covers the gate structure and the epitaxial layer. The opening is in the interlayer dielectric layer. The germanium cap fills the bottom of the opening and has a germanium concentration in excess of 50 atomic %. The contact plug is disposed on the germanium cap in the opening.

Abstract translation: FinFET包括鳍状结构，栅极结构，外延层，层间介电层，开口，锗帽和接触插塞。 鳍状结构设置在基板上。 栅极结构覆盖鳍状结构的一部分。 外延层设置在与栅极结构相邻的鳍状结构上。 层间绝缘层覆盖栅极结构和外延层。 开口位于层间绝缘层中。 锗帽填充开口的底部，锗浓度超过50原子％。 接触插头设置在开口中的锗帽上。