公开(公告)号：US5602417A

公开(公告)日：1997-02-11

申请号：US312386

申请日：1994-09-26

Applicant: Flavio Villa

Inventor： Flavio Villa

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L27/082 ,  H01L27/102

CPC classification number: H01L29/1004

Abstract: A low-noise NPN transistor comprising a cut-off region laterally surrounding, at a given distance, the emitter region in the surface portion of the transistor and of such conductivity as to practically turn off the surface portion of the transistor, so that the transistor operates mainly in the bulk portion. The cut-off region is formed by a P ring astride a P.sup.- type well region and the epitaxial layer.

Abstract translation: 一种低噪声NPN晶体管，其包括在晶体管的表面部分中以给定距离横向包围发射极区域的截止区域，并且具有实际上关闭晶体管的表面部分的导电性，使得晶体管 主要在批量部分运行。 截止区域由跨越P型阱区域的P环和外延层形成。

公开(公告)号：USRE35442E

公开(公告)日：1997-02-04

申请号：US183011

申请日：1994-01-14

Applicant: Claudio Contiero ,  Paola Galbiati ,  Lucia Zullino

Inventor： Claudio Contiero ,  Paola Galbiati ,  Lucia Zullino

IPC: H01L27/06 ,  H01L29/735 ,  H01L29/76

CPC classification number: H01L27/0623 ,  H01L29/735

Abstract: A high density, mixed technology integrated circuit comprises CMOS structures and bipolar lateral transistors, the electrical efficiency and Early voltage of which are maintained high by forming "well" regions through the collector area. The operation determines the formation of a "collector extension region" extending relatively deep within the epitaxial layer so as to intercept the emitter current and gather it to the collector, subtracting it from dispersion toward the substrate through the adjacent isolation junctions surrounding the region of the lateral bipolar transistor. Under comparable conditions, the ratio between IcIsubstrate is incremented from about 8 to about 300 and the Early voltage from about 20V to about 100V. The V.sub.CEO, BV.sub.CBO and BV.sub.CES voltages are also advantageously increased by the presence of said "well" region formed in the collector zone.

Abstract translation: 高密度，混合技术的集成电路包括CMOS结构和双极横向晶体管，通过在收集器区域形成“阱”区域，电效率和早期电压保持较高。 该操作确定在外延层内形成相对较深的“集电极延伸区域”，以便截取发射极电流并将其收集到集电极，并将其从色散向衬底通过围绕着该区域的相邻隔离结 横向双极晶体管。 在可比较的条件下，IcI衬底之间的比例从大约8增加到大约300，而早期电压从大约20V增加到大约100V。 VCEO，BVCBO和BVCES电压也有利地通过在收集器区域中形成的所述“阱”区域的存在来增加。

公开(公告)号：US5600590A

公开(公告)日：1997-02-04

申请号：US477302

申请日：1995-06-07

Applicant: Paolo Ghezzi ,  Alfonso Maurelli

Inventor： Paolo Ghezzi ,  Alfonso Maurelli

IPC: H01L21/8247 ,  H01L21/329 ,  H01L27/06 ,  H01L27/115 ,  H01L29/866 ,  G11C13/00

CPC classification number: H01L29/66106 ,  H01L27/0629 ,  H01L29/866 ,  Y10S148/174 ,  Y10S438/983

Abstract: A process for the manufacture of an integrated voltage limiter and stabilizer component in a flash EEPROM memory device comprises a step of formation of an N type lightly doped well on a single-crystal silicon substrate; a step of formation of an active area on the surface of said N type well; a step of growth of a thin gate oxide layer over said active area; a step of implantation of a first heavy dose of N type dopant into said N type well to obtain an N type region; a step of implantation of a second heavy dose, higher than said first heavy dose, of N type dopant into said N type region to obtain an N+contact region to both the N type well and said N type region; a step of implantation of a third heavy dose, higher than said first heavy dose, of P type dopant into said N type region to form a P+ region.

Abstract translation: 一种用于在快速EEPROM存储器件中制造集成式限压器和稳定器部件的方法包括在单晶硅衬底上形成N型轻掺杂阱的步骤; 在所述N型井的表面上形成活性区的步骤; 在所述有源区上生长薄栅氧化层的步骤; 将第一重剂量的N型掺杂剂注入到所述N型阱中以获得N型区域的步骤; 向所述N型区域注入高于所述第一重剂量的N型掺杂剂的第二重剂量以获得N型阱和所述N型区域的N +接触区域的步骤; 将高于所述第一重剂量的P型掺杂剂的第三重剂量植入所述N型区域以形成P +区域的步骤。

公开(公告)号：US5598028A

公开(公告)日：1997-01-28

申请号：US468282

申请日：1995-06-06

Applicant: Aldo Losavio ,  Maurizio Bacchetta

Inventor： Aldo Losavio ,  Maurizio Bacchetta

IPC: H01L21/8247 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L29/788 ,  H01L29/792 ,  H01L23/58 ,  H01L23/48

CPC classification number: H01L21/76819 ,  H01L21/31051 ,  H01L2924/0002

Abstract: A planarization process for the manufacturing of highly-planar interlayer dielectric thin films in integrated circuits, particularly in non-volatile semiconductor memory devices, comprises the steps of: forming a first barrier layer over a semiconductor substrate wherein integrated devices have been previously obtained; forming a second layer of oxide containing phosphorous and boron over the first undoped oxide the concentration of boron being lower than the concentration of phosphorous; forming a third layer of oxide containing phosphorous and boron over the second oxide layer, the concentration of phosphorous being lower than or equal to the concentration of boron; performing a thermal process at a temperature sufficient to melt the third oxide layer, to obtain a planar surface.

Abstract translation: 用于制造集成电路中特别是非易失性半导体存储器件中的高平面层间电介质薄膜的平面化方法包括以下步骤：在半导体衬底上形成第一势垒层，其中先前获得了集成器件; 在第一未掺杂氧化物上形成含有磷和硼的第二氧化物层，硼的浓度低于磷的浓度; 在第二氧化物层上形成含有磷和硼的第三氧化物层，磷的浓度低于或等于硼的浓度; 在足以熔化第三氧化物层的温度下进行热处理，以获得平坦表面。

公开(公告)号：US5597750A

公开(公告)日：1997-01-28

申请号：US474735

申请日：1995-06-07

Applicant: Federico Pio ,  Carlo Riva ,  Silvia Lucherini

Inventor： Federico Pio ,  Carlo Riva ,  Silvia Lucherini

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11526 ,  G11C16/04 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11541

Abstract: A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells including plural rows and columns, with each row being provided with a word line and a control gate line and each column having a bit line; the bit lines, moreover, are gathered into groups or bytes of simultaneously addressable adjacent lines. Each cell in the matrix incorporates a floating gate transistor which is coupled to a control gate, connected to the control gate line, and is connected serially to a selection transistor; also, the cells of each individual byte share their respective source areas, which areas are structurally independent for each byte and are led to a corresponding source addressing line extending along a matrix column.

Abstract translation: 一种用于EEPROM存储器单元的矩阵的电路结构，其包括包括多行和列的单元矩阵，每行具有字线和控制栅极线，每列具有位线; 此外，位线被收集成同时可寻址的相邻线的组或字节。 矩阵中的每个单元都包含一个浮动栅极晶体管，它连接到控制栅极，连接到控制栅极线，并串联连接到选择晶体管; 每个单独字节的单元也共享它们各自的源区域，哪些区域对于每个字节在结构上是独立的，并且被引导到沿着矩阵列延伸的对应的源寻址行。

公开(公告)号：US5590075A

公开(公告)日：1996-12-31

申请号：US479081

申请日：1995-06-07

Applicant: Stefano Mazzali

Inventor： Stefano Mazzali

IPC: G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/10 ,  G11C29/24 ,  G11C29/52 ,  G11C29/56 ,  G11C7/00

CPC classification number: G11C29/82 ,  G11C29/10 ,  G11C29/24 ,  G11C29/52

Abstract: A method for testing an electrically erasable and programmable memory device comprising a matrix of memory cells and redundancy memory cells for functionally substituting defective memory cells, comprises the steps of: programing all the memory cells of the memory device; submitting all the memory cells of the memory device to a preliminary electrical erasure for a time much shorter than an average erasing time of the memory cells; reading the information stored in all the memory cells of the memory device; memorizing the addresses of defective memory cells which have been read as erased memory cell; storing the addresses of the defective memory cells in redundancy registers associated to redundancy memory cells which must substitute the defective memory cells.

Abstract translation: 一种用于测试电可擦除和可编程的存储器件的方法，包括存储器单元矩阵和功能代替有缺陷存储器单元的冗余存储单元，包括以下步骤：对存储器件的所有存储单元进行编程; 将存储器件的所有存储单元提交到比存储器单元的平均擦除时间短得多的时间的初步电擦除; 读取存储在存储设备的所有存储单元中的信息; 存储被读取为已擦除存储单元的有缺陷的存储单元的地址; 将有缺陷的存储器单元的地址存储在冗余存储器单元中，该冗余寄存器与必须替代有缺陷的存储器单元的冗余存储器单元相关联。

公开(公告)号：US5586077A

公开(公告)日：1996-12-17

申请号：US366212

申请日：1994-12-29

Applicant: Marco Olivo ,  Silvia Padoan

Inventor： Marco Olivo ,  Silvia Padoan

IPC: G11C17/00 ,  G06F1/24 ,  G11C16/06 ,  G11C16/30 ,  G11C7/00

CPC classification number: G11C16/30

Abstract: A method for generating a reset signal in an electrically programmable non-volatile storage device of a type which comprises a matrix of memory cells and a control logic portion being supplied a supply voltage and a programming voltage, and a threshold detection circuit adapted to detect a decrease in the supply voltage, provides for the signal applied to the control logic to be obtained as a change-over function between the output signal from the threshold detector and a reset signal generated during the power-on transient of the device.

Abstract translation: 一种用于在电可编程非易失性存储装置中产生复位信号的方法，该方法包括存储单元矩阵和提供电源电压和编程电压的控制逻辑部分，以及阈值检测电路， 降低电源电压，提供作为在来自阈值检测器的输出信号与在器件的上电瞬变期间产生的复位信号之间的转换功能而获得的控制逻辑的信号。

公开(公告)号：US5585794A

公开(公告)日：1996-12-17

申请号：US224673

申请日：1994-04-07

Applicant: Fabrizio Airoldi ,  Alessandro Cremonesi

Inventor： Fabrizio Airoldi ,  Alessandro Cremonesi

IPC: H03H17/06 ,  H03M7/00

CPC classification number: H03H17/028 ,  H03H17/0628

Abstract: An electronic device for the automatic conversion of sampling frequencies, being a type adapted to convert a predetermined frequency of a sampled input signal to a desired frequency of an output signal. The device is comprised of:a phase detector being input both the input frequency and the output frequency; a decoder block associated with the detector to determine an interpolation coefficient; an interpolation filter having a digital input for encoding the sampling signal and receiving the input frequency on the one side, and a digital signal representative of the interpolation coefficient on the other side; and a synchronizer connected after the filter and being input both said input and output frequencies, the synchronizer having a digital output for encoding the converted sampling signal.

Abstract translation: 一种用于自动转换采样频率的电子设备，其是适于将采样的输入信号的预定频率转换为输出信号的期望频率的类型。 该装置包括：相位检测器输入输入频率和输出频率; 与检测器相关联的解码器块以确定内插系数; 内插滤波器，具有用于对采样信号进行编码并在一侧接收输入频率的数字输入和表示另一侧的插值系数的数字信号; 以及在所述滤波器之后连接并同时输入所述输入和输出频率的同步器，所述同步器具有用于对所转换的采样信号进行编码的数字输出。

公开(公告)号：US5581563A

公开(公告)日：1996-12-03

申请号：US379317

申请日：1995-01-24

Applicant: Luigi Penza ,  Michele Favalli ,  Bruno Ricco

Inventor： Luigi Penza ,  Michele Favalli ,  Bruno Ricco

IPC: G01R31/26 ,  G01R31/28 ,  G01R31/30 ,  G01R31/317 ,  H01L21/66 ,  G06F11/00

CPC classification number: G01R31/3008 ,  G01R31/3004 ,  G01R31/3012 ,  G01R31/31704

Abstract: A DFT technique for the detection of bridging faults in CMOS and BiCMOS logic ICs, employs purposely integrated monitoring inverters, driven by signal nodes of the functional circuits to be tested, for revealing the presence of intermediate voltages of a critical value. The monitoring inverters are supplied through a dedicated shadow line that is connected to either one of the supply rails of the functional circuits through a load: a resistance, for a static implementation, or a capacitor, for a dynamic (clocked) implementation. Absence of series connected built-in current sensors (BICSs) avoids degradation of the performance of the functional circuits and is compatible with scaling down of the power supply and with on-line testing techniques. Only critical bridging faults may be reliably and selectively detected, thus reducing the number of rejects, failing a conventional IDDQ test. In a modified embodiment, a DFT scheme of the invention may be adapted to reveal also stuck-at faults, by connecting together the output nodes of certain monitoring inverters to create activatable current paths from a test node (shadow line) and a supply rail of the IC.

Abstract translation: 用于检测CMOS和BiCMOS逻辑IC中的桥接故障的DFT技术，采用由要测试的功能电路的信号节点驱动的专门集成的监控逆变器，用于显示临界值的中间电压的存在。 监控逆变器通过专用阴影线提供，专用阴影线通过负载：用于静态实现的电阻或用于动态（时钟））实现的电阻连接到功能电路的任一个的电源轨。 没有串联连接的内置电流传感器（BICS）避免了功能电路性能的恶化，并与电源的缩小以及在线测试技术兼容。 只有关键的桥接故障可以被可靠和有选择地检测，从而减少了拒绝的次数，不能进行常规的IDDQ测试。 在修改的实施例中，本发明的DFT方案可以适于通过将某些监控逆变器的输出节点连接在一起以产生来自测试节点（阴影线）和供电轨的可激活电流路径 IC。

公开(公告)号：US5572156A

公开(公告)日：1996-11-05

申请号：US529883

申请日：1995-09-18

Applicant: Claudio Diazzi ,  Fabrizio Martignoni ,  Mario Tarantola

Inventor： Claudio Diazzi ,  Fabrizio Martignoni ,  Mario Tarantola

IPC: H02P7/29 ,  H03K3/356 ,  H03K17/06 ,  H03K17/16 ,  H03K17/687 ,  H03K3/00

CPC classification number: H03K3/356113 ,  H03K17/063 ,  H03K17/161 ,  H03K17/687

Abstract: A control circuit for a power transistor, connected between two supply terminals in series with a load. The control circuit comprises a control logic circuit which produces a signal at two levels with respect to a reference terminal, a level shifter connected between the control circuit and the power transistor, which produces a signal at two levels relative to the node between the power transistor and the load. The level shifter comprises a flip-flop the output of which controls the power transistor, and an electronic switch, for example a MOSFET transistor, connected between the "set" input of the flip-flop and the node and controlled by the "reset" input of the flip-flop in such a way as to be closed when the "reset" input is greater, by a predetermined value, than that of the node. The electronic switch prevents the parasitic current flowing through the set and reset inputs from erroneously switching the power transistor.

Abstract translation: 用于功率晶体管的控制电路，连接在与负载串联的两个电源端子之间。 该控制电路包括控制逻辑电路，该控制逻辑电路相对于参考端产生两个电平的信号，连接在控制电路和功率晶体管之间的电平转换器，其产生相对于功率晶体管 和负载。 电平移位器包括其输出端控制功率晶体管的触发器和连接在触发器的“设置”输入和节点之间并由“复位”控制的电子开关，例如MOSFET晶体管， 触发器的输入以当“复位”输入比节点的输入大一预定值时被关闭。 电子开关防止流过设定和复位输入的寄生电流错误地切换功率晶体管。