公开(公告)号：US09543214B2

公开(公告)日：2017-01-10

申请号：US14526081

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

Inventor： Denis Rideau ,  Elise Baylac ,  Emmanuel Josse ,  Pierre Morin ,  Olivier Nier

IPC: H01L21/8234 ,  H01L21/84 ,  H01L21/762 ,  H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/324 ,  H01L27/12

CPC classification number: H01L21/823481 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/3081 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/7846 ,  H01L29/7847

Abstract: The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.

Abstract translation: 本发明涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层的半导体结构中形成在第一方向上的一个或多个第一隔离沟槽，以限定待形成的至少一个晶体管的第一维度 在所述半导体结构中; 在所述半导体结构中，在第二方向上形成用于限定所述至少一个晶体管的第二尺寸的一个或多个第二隔离沟槽，所述第一和第二隔离沟槽至少部分地填充有绝缘材料; 并且在形成第二隔离沟槽之前或之后，通过将第一材料的原子注入到第一隔离沟槽中来降低第一隔离沟槽中的绝缘材料的粘度，其中第一材料的原子未被注入第二隔离层 沟渠

公开(公告)号：US20170003571A1

公开(公告)日：2017-01-05

申请号：US15068704

申请日：2016-03-14

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Jean-Francois Carpentier ,  Patrick LeMaitre ,  Denis Pache

IPC: G02F1/225 ,  G02F1/025 ,  G02F1/01

CPC classification number: G02F1/2255 ,  G02F1/0123 ,  G02F1/025 ,  G02F1/2257 ,  G02F2001/212

Abstract: An integrated modulator of the Mach-Zehnder type includes two optical arms containing waveguides with PN junctions and biasing circuits for reverse biasing the PN junctions in response to a control signal. The two optical arms are situated within a semiconductor substrate of a first element that also has an interconnection region. The biasing circuits are situated, in part, within a substrate of a second element that also contains an interconnection region. The first and second elements are rigidly attached to each other via their respective interconnection regions.

Abstract translation: Mach-Zehnder型集成调制器包括两个含有PN结的波导的光学臂和用于响应控制信号反向偏置PN结的偏置电路。 两个光学臂位于也具有互连区域的第一元件的半导体衬底内。 偏置电路部分地位于也包含互连区域的第二元件的衬底内。 第一和第二元件通过其相应的互连区域彼此刚性连接。

公开(公告)号：US09530817B2

公开(公告)日：2016-12-27

申请号：US14953973

申请日：2015-11-30

Applicant: STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Michel Marty ,  Laurent Frey

IPC: H01L29/06 ,  H01L27/14 ,  H01L31/062 ,  H01L21/00 ,  H01L27/146 ,  H01L31/0232 ,  H01L31/107 ,  H01L31/0352

CPC classification number: H01L27/14685 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L31/02327 ,  H01L31/035236 ,  H01L31/107

Abstract: A back side illumination photodiode includes a light-receiving back side surface of a semiconductor material substrate. An area of the light-receiving back side surface includes a recess. The recess is filled with a material having an optical index that is lower than an optical index of the semiconductor material substrate. Both the substrate and the filling material are transparent to an operating wavelength of the photodiode. The recess may be formed to have a ring shape.

公开(公告)号：US20160370610A1

公开(公告)日：2016-12-22

申请号：US15251236

申请日：2016-08-30

Applicant: STMICROELECTRONICS SA

Inventor： JEAN-ROBERT MANOUVRIER

IPC: G02F1/025 ,  G02F1/01

CPC classification number: G02F1/025 ,  G02F1/0123 ,  G02F1/225 ,  G02F1/2255

Abstract: A semiconductor electro-optical phase shifter may include a substrate, an optical waveguide segment (12) formed on the substrate, and first and second zones of opposite conductivity types configured to form a first bipolar junction perpendicular to the substrate. The phase shifter may also include a dynamic control structure configured to reverse bias the first junction and a static control structure configured to direct a quiescent current in the second zone, parallel to the first junction.

公开(公告)号：US09507181B2

公开(公告)日：2016-11-29

申请号：US15198114

申请日：2016-06-30

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Robert Manouvrier

IPC: G02F1/025 ,  G02F1/225 ,  G02B6/12 ,  H04B10/54 ,  H04B10/548

CPC classification number: G02F1/025 ,  G02B6/12 ,  G02F1/2257 ,  H04B10/548

Abstract: A semiconductor electro-optical phase shifter may include an optical action zone configured to be inserted in an optical waveguide, and a bipolar transistor structure configured so that, in operation, collector current of the bipolar transistor structure crosses the optical action zone perpendicular to the axis of the optical waveguide.

Abstract translation: 半导体电光移相器可以包括被配置为插入在光波导中的光学作用区域和双极晶体管结构，其被配置为使得在操作中双极晶体管结构的集电极电流与垂直于轴线的光学作用区域相交 的光波导。

公开(公告)号：US20160322276A1

公开(公告)日：2016-11-03

申请号：US15204488

申请日：2016-07-07

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Bar ,  Alisee Taluy ,  Olga Kokshagina

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/3675 ,  H01L21/32139 ,  H01L21/4853 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76897 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14519 ,  H01L2224/29013 ,  H01L2224/29082 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/3015 ,  H01L2224/30519 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83801 ,  H01L2224/9211 ,  H01L2924/12042 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

公开(公告)号：US09473097B2

公开(公告)日：2016-10-18

申请号：US14515342

申请日：2014-10-15

Applicant: STMicroelectronics SA

Inventor： Emmanuel Rouat

IPC: H03F1/34 ,  H03G3/30 ,  H03F3/45 ,  H03G1/00 ,  H03G3/00

CPC classification number: H03G3/30 ,  H03F3/45071 ,  H03F2203/45178 ,  H03F2203/45202 ,  H03F2203/45336 ,  H03F2203/45528 ,  H03G1/0088 ,  H03G3/001

Abstract: A resistive ladder has first, second and third resistors coupled in series between first and second voltage terminals. A first node of the first resistor is coupled to the first voltage terminal and a first node of the third resistor is coupled to the second voltage terminal. A voltage selection unit has a first input coupled to a first node of the second resistor and a second input coupled to a second node of the second resistor and is adapted to selectively couple one of the first and second inputs to an output node of said resistive ladder. The resistive ladder also includes a first switch coupled between a second node of the third resistor and the second voltage terminal.

Abstract translation: 电阻梯具有在第一和第二电压端子之间串联耦合的第一，第二和第三电阻器。 第一电阻器的第一节点耦合到第一电压端子，并且第三电阻器的第一节点耦合到第二电压端子。 电压选择单元具有耦合到第二电阻器的第一节点的第一输入和耦合到第二电阻器的第二节点的第二输入，并且适于选择性地将第一和第二输入中的一个耦合到所述电阻的输出节点 阶梯。 电阻梯还包括耦合在第三电阻器的第二节点和第二电压端子之间的第一开关。

公开(公告)号：US09464933B1

公开(公告)日：2016-10-11

申请号：US14920373

申请日：2015-10-22

Applicant: STMicroelectronics SA

Inventor： Hani Sherry

IPC: G01J1/42 ,  G01J1/44

CPC classification number: G01J1/4228 ,  G01J1/42 ,  G01J1/44 ,  H03K3/0315

Abstract: The present disclosure concerns a high frequency imager including a pixel matrix, each pixel including a high frequency oscillator, a transmission line positioned at a distance from an active surface of the imager smaller than the operating wavelength of the oscillator, a first end of the line being coupled to the oscillator, and a read circuit coupled to a second end of the line.

Abstract translation: 本公开涉及包括像素矩阵的高频成像器，每个像素包括高频振荡器，位于与成像器的有源表面相距一定距离处的传输线小于振荡器的工作波长，线的第一端 耦合到所述振荡器，以及耦合到所述线路的第二端的读取电路。

公开(公告)号：US09461641B2

公开(公告)日：2016-10-04

申请号：US14062455

申请日：2013-10-24

Applicant: STMicroelectronics SA

Inventor： Severin Trochut ,  Emilie Rigal ,  Fabrice Blisson ,  Frederic Hasbani ,  Nicolas Seller

IPC: H03K17/687 ,  H03K17/22 ,  G06F1/32

CPC classification number: H03K17/6871 ,  G06F1/3287 ,  H03K17/22 ,  Y02D10/171 ,  Y10T307/76

Abstract: A chain of switches is connected between a first power supply line coupled to a first voltage and a second power supply line coupled to the sector. These switches are controllable by a control signal. The control signal is propagated from a first end of the first chain towards a second end of the first chain without control of the switches during this first propagation. The control signal is then propagated in the reverse direction from the second end towards the first end with a control of the switches during this second propagation starting from a group of at least one switch situated at the second end. There is a detection of the arrival of the control signal at the first end of the chain at the end of its propagation in the reverse direction.

Abstract translation: 一连串的开关连接在耦合到第一电压的第一电源线和耦合到扇区的第二电源线之间。 这些开关由控制信号控制。 控制信号从第一链的第一端传播到第一链的第二端，而在该第一次传播期间不控制开关。 然后，控制信号从第二端朝向第一端的相反方向传播，在第二次传播期间通过位于第二端的一组至少一个开关的一组开关进行控制。 在反向传播结束时，检测到链的第一端处的控制信号的到达。

公开(公告)号：US20160284807A1

公开(公告)日：2016-09-29

申请号：US14930324

申请日：2015-11-02

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： David Petit ,  Frederic Monsieur ,  Xavier Federspiel ,  Gregory Bidal

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/10 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/42364 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L27/127 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/7838

Abstract: A substrate of the silicon-on-insulator type is formed from an initial substrate of the silicon-on-insulator type having a semiconductor film on top of a buried insulating layer itself situated on top of a carrier substrate. A localized modification of a thickness of the semiconductor film is made so as to form a semiconductor film having different thicknesses in different regions.

Abstract translation: 绝缘体上硅型的衬底由绝缘体上硅型的初始衬底形成，其中半导体膜位于位于载体衬底顶部的掩埋绝缘层本身的顶部上。 制造半导体膜的厚度的局部修改以便形成在不同区域中具有不同厚度的半导体膜。