公开(公告)号：US20250007890A1

公开(公告)日：2025-01-02

申请号：US18759498

申请日：2024-06-28

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Robert Noel Bielby

IPC: H04L9/40 ,  G06F8/65 ,  G06F21/57

Abstract: Methods, systems, and devices for security configurations for zonal computing architecture are described. A zonal computing system in a vehicle may be associated with multiple zones. The zonal computing system may include devices (e.g., sensors, actuators) that interact with the vehicle or an environment associated with the vehicle. A memory system included in the zonal computing system may authenticate whether a device associated with a zone is a trusted device and enable or restrict communications with the device based on the authentication. For example, the zonal computing system may include a central processor that communicates with a remote server and the multiple zones and may include a gateway processor coupled with the central processor and the device and associated with the zone. Based on whether the device is trusted, the memory system may enable or restrict communications between the central processer and the device and routed through the gateway processor.

公开(公告)号：US20250006324A1

公开(公告)日：2025-01-02

申请号：US18883624

申请日：2024-09-12

Applicant: Micron Technology, Inc.

Inventor： Libo Wang ,  Xiao Li ,  Bethany M. Grentz ,  Sumana Adusumilli ,  Carla L. Christensen

IPC: G16H10/60 ,  G01W1/10 ,  G16H20/70

Abstract: Systems for weather sensing and forecasting, and associated devices and methods, are disclosed herein. In some embodiments, a system for predicting a subject's perception of weather conditions is provided. The system can generate an individual profile for the subject, the individual profile including health information of the subject. The system can receive weather data including a first weather condition for a target location. The system can compare the individual profile to a plurality of different user profiles to identify one or more similar user profiles. Each similar user profile can (1) be associated with a user having similar health information as the subject, and (2) include weather perception data indicating how the user perceived a set of second weather conditions. Based on the weather data and the similar user profile(s), the system can generate a prediction of the how the subject will perceive the first weather condition.

公开(公告)号：US20250006292A1

公开(公告)日：2025-01-02

申请号：US18440619

申请日：2024-02-13

Applicant: Micron Technology, Inc.

Inventor： Taylor Alu ,  Nicola Ciocchini ,  Shyam Sunder Raghunathan ,  Guang Hu ,  Walter Di Francesco ,  Umberto Siciliani ,  Violante Moschiano ,  Karan Banerjee

IPC: G11C29/52 ,  G11C16/20 ,  G11C16/34

Abstract: A method includes detecting a change in a memory control signal of a memory device including memory blocks, determining based at least on the change in the memory control signal that the memory device is in a stable state, and responsive to determining that the memory device is in the stable state, associating a voltage offset bin with at least one memory block of the memory device.

公开(公告)号：US20250006275A1

公开(公告)日：2025-01-02

申请号：US18749198

申请日：2024-06-20

Applicant: Micron Technology, Inc.

Inventor： Shyam Sunder Raghunathan ,  Akira Goda ,  Kishore K. Muchherla

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/26

Abstract: An apparatus can comprise a memory array comprising multiple erase blocks coupled to a same plurality of strings of memory cells. Control circuitry can be configured to: receive a command corresponding to a sensing operation to be performed on a selected access line of a first group of access lines corresponding to a first erase block; and determine an adjusted sense voltage to be applied to the selected access line in association with performing the sensing operation. The adjusted sense voltage is based on: a quantity of the first group of access lines that are programmed; or a quantity of the second group of access lines that are programmed; or both.

公开(公告)号：US20250006251A1

公开(公告)日：2025-01-02

申请号：US18829647

申请日：2024-09-10

Applicant: Micron Technology, Inc.

Inventor： Aliasger T. Zaidy ,  Glen E. Hush ,  Sean S. Eilert ,  Kunal R. Parekh

IPC: G11C11/4093 ,  G06F3/06 ,  G06F13/16 ,  G06F13/28 ,  G11C7/08 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G16B30/00 ,  G16B50/10 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data. The inputs and the outputs to the VV units can be configured based on a mode of the logic die.

公开(公告)号：US20250004875A1

公开(公告)日：2025-01-02

申请号：US18829593

申请日：2024-09-10

Applicant: Micron Technology, Inc.

Inventor： Keun Soo Song ,  Kang-Yong Kim ,  Hyun Yoo Lee

IPC: G06F11/10 ,  G06F3/06

Abstract: Described apparatuses and methods provide configurable error correction code (ECC) circuitry and schemes that can utilize a shared ECC engine between multiple memory banks of a memory, including a low-power double data rate (LPDDR) memory. A memory device may include one or more dies with multiple memory banks. The configurable ECC circuitry can use an ECC engine that services a memory bank by producing ECC values based on data stored in the memory bank when data-masking functionality is enabled. When data-masking functionality is disabled, the configurable ECC circuitry can use the shared ECC engine that services at least two memory banks by producing ECC values with a larger quantity of bits based on respective data stored in the at least two memory banks. By using the shared ECC engine responsive to the data-masking functionality being disabled, the ECC functionality can provide higher data reliability with lower die area utilization.

公开(公告)号：US20250004664A1

公开(公告)日：2025-01-02

申请号：US18765072

申请日：2024-07-05

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello

IPC: G06F3/06

Abstract: Methods, systems, and devices for read latency and suspend modes are described. A memory system may operate in a first mode of operation associated with a first set of access operations including executing read operations, executing write operations, and suspending write operations. The memory system may receive, from a host system, an indication to switch to a second mode of operation associated with a decreased latency for executing write operations based on limiting a suspension of write operations. For example, the host system may transmit a command including the indication to switch to the second mode of operation. In another example, the host system may write a value to a register at the memory system including the indication to switch to the second mode of operation. Based on receiving the indication from the host system, the memory system may then operate according to the second mode of operation.

公开(公告)号：US20250004659A1

公开(公告)日：2025-01-02

申请号：US18643936

申请日：2024-04-23

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F3/06

Abstract: Methods, systems, and devices for techniques for coupled host and memory dies are described. A controller of a memory system may facilitate data rearrangement within a block-addressable memory device based on metadata associated with prefetching data to a byte-addressable memory device or to a host system. For example, the controller may utilize the metadata and various access commands to rearrange associated data within the block-addressable memory device such that the data is written to a singular superblock of the block-addressable memory device. In some examples, one or more counters may be utilized by the controller to determine whether to rearrange the data within the block-addressable memory device.

公开(公告)号：US12183685B2

公开(公告)日：2024-12-31

申请号：US18487879

申请日：2023-10-16

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege

IPC: H01L23/538 ,  G11C5/06 ,  H10B12/00

Abstract: A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises memory arrays comprising memory cells comprising access devices and storage node devices, digit lines coupled to the access devices and extending in a first direction to a digit line exit region, and word lines coupled to the access devices and extending in a second direction to a word line exit region. The second microelectronic device structure comprises control logic devices over and in electrical communication with the memory cells. The microelectronic device further comprises contact structures individually in contact with the digit lines in the digit line exit region and in electrical communication with at least some of the control logic devices, at least one of the contact structures comprising a first cross-sectional area at an interface of the first microelectronic device structure and the second microelectronic device structure, and a second cross-sectional area at an interface of one of the digit lines and the at least one of the contact structures, the second cross-sectional area smaller than the first cross-sectional area. Related microelectronic devices, memory devices, electronic systems, and methods are also described.

公开(公告)号：US12183407B2

公开(公告)日：2024-12-31

申请号：US17736902

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Umberto Siciliani ,  Tao Liu ,  Ting Luo ,  Dionisio Minopoli ,  Giuseppe D'Eliseo ,  Giuseppe Ferrari ,  Walter Di Francesco ,  Antonino Pollio ,  Luigi Esposito ,  Anna Scalesse ,  Allison J. Olson ,  Anna Chiara Siviero

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

Abstract: Methods, systems, and devices for setting switching for single-level cells (SLCs) are described. A memory system may receive an access command from a host. The access command may correspond to an SLC block or to a multiple-level cell block. If the access command corresponds to an SLC block, the memory system may modify the access command to include one or more bits indicating a setting to use for performing the access operation corresponding to the access command. The setting may define one or more operating parameters for performing the access operation. The memory system may use bits to indicate the setting that are used to indicate a page address for multiple-level cell blocks. The memory system may issue the access command to a memory device, which may perform the access operation using the setting indicated in the one or more bits included by the memory system.