公开(公告)号：US20240300808A1

公开(公告)日：2024-09-12

申请号：US18596223

申请日：2024-03-05

Applicant: Analog Devices, Inc.

Inventor： Kemiao Jia ,  Gaurav Vohra ,  Xin Zhang ,  Christine H. Tsau ,  Chen Yang ,  Andrew Proudman ,  Matthew Kent Emsley ,  George M. Molnar, II ,  Nikolay Pokrovskiy ,  Ali Mohammed Shakir ,  Michael Judy

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00666 ,  B81B3/0072 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/0315 ,  B81C2201/0111 ,  B81C2201/019

Abstract: Described herein are manufacturing techniques for achieving stress isolation in microelectromechanical systems (MEMS) devices that involve isolation trenches formed from the backside of the substrate. The techniques described herein involve etching a trench in the bottom side of the substrate subsequent to forming a MEMS platform, and processing the MEMS platform to form a MEMS device on the top side of the substrate subsequent to etching the trench.

公开(公告)号：US20240297622A1

公开(公告)日：2024-09-05

申请号：US18262553

申请日：2022-02-22

Applicant: Analog Devices, Inc.

Inventor： Christopher Mayer ,  Tao Yu ,  Gregory Patrick Davis

IPC: H03F1/32 ,  H03F3/189 ,  H03F3/24

CPC classification number: H03F1/3247 ,  H03F3/189 ,  H03F3/24

Abstract: Apparatus and methods for pre-distorting a radio frequency transmit signal based on local oscillator clock shaping are disclosed. In certain embodiments, one or more clock signals generated by a local oscillator and used for mixing in a transceiver are shaped to account for non-linearity of a power amplifier that amplifies the radio frequency transmit signal. Such pre-distortion can be performed in addition to or alternatively to performing digital pre-distortion on a digital representation of the radio frequency transmit signal.

公开(公告)号：US20240275377A1

公开(公告)日：2024-08-15

申请号：US18439756

申请日：2024-02-12

Applicant: ANALOG DEVICES, INC.

Inventor： Rajasekhar Nagulapalli

IPC: H03K17/30 ,  H03F3/45 ,  H03K19/00 ,  H03K19/0185

CPC classification number: H03K17/302 ,  H03F3/45183 ,  H03F3/45273 ,  H03K19/0005 ,  H03K19/018528 ,  H03F2200/261

Abstract: Presented are systems and methods for high-swing push-pull assisted Voltage Mode Logic (VML) driver circuits that enhance output voltage amplitude to improve efficiency and performance in electronic applications. In embodiments, this is accomplished by utilizing a primary current generator circuit that is powered by a supply voltage to generate a primary current. The primary current is provided, through a switching circuit, to an output node that, in response to an input signal, generates a first output voltage. Further, a supplementary current generator circuit is coupled to the switching circuit to generate a secondary current. The combination of the primary and secondary currents increases the amplitude of the first output voltage, thereby enabling the VML driver circuit to deliver enhanced performance, particularly in applications requiring precise voltage control and high efficiency.

公开(公告)号：US12061977B2

公开(公告)日：2024-08-13

申请号：US17675617

申请日：2022-02-18

Applicant: Analog Devices, Inc.

Inventor： Eric G. Nestler ,  Naveen Verma ,  Hossein Valavi

IPC: G06N3/065 ,  G06N3/045 ,  G06N3/048 ,  G06N3/06 ,  G11C11/54

CPC classification number: G06N3/065 ,  G06N3/045 ,  G06N3/048 ,  G06N3/061 ,  G11C11/54

Abstract: Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as memory bit cells, transistors configured to perform in-memory computing using the memory bit cells, capacitors configured to store a result of in-memory computing from the memory bit cells, and switches, wherein, based on a setting of each of the switches, the charges on at least a portion of the plurality of capacitors are shorted together. Shorting together the plurality of capacitors yields a computation result.

公开(公告)号：US12031939B2

公开(公告)日：2024-07-09

申请号：US17827619

申请日：2022-05-27

Applicant: Analog Devices, Inc.

Inventor： Mohamed Azize ,  Shekhar Bakshi

IPC: G01N27/414 ,  G01N27/30 ,  H01L29/16 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: G01N27/4145 ,  G01N27/301 ,  G01N27/414 ,  H01L29/42316 ,  H01L29/66045 ,  H01L29/66075 ,  H01L29/1606 ,  H01L29/4908

Abstract: Provided are methods of manufacturing comprising providing a FET base structure, the FET base structure comprising a substrate, a drain and a source; and providing a channel layer on the FET base structure; and providing a first layer on the FET base structure. The first layer comprises a one-dimensional or two-dimensional material and is arranged on an upper surface of the channel layer so as to form a sensing surface of the FET. The step of providing the channel layer comprises forming the channel layer and subsequently transferring the channel layer onto the FET base structure. Alternatively or additionally, the step of providing the first layer on the FET base structure comprises forming the first layer and subsequently transferring the first layer onto the FET base structure.

公开(公告)号：US20240213239A1

公开(公告)日：2024-06-27

申请号：US18069777

申请日：2022-12-21

Applicant: Analog Devices, Inc.

Inventor： James G. Fiorenza ,  Daniel Piedra

IPC: H01L27/02 ,  H01L29/20 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L27/0255 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/45 ,  H01L29/66462 ,  H01L29/7786

Abstract: Techniques to integrate a p-n diode with a GaN HEMT, such as in a silicon carbide (SiC) substrate. The p-n diode provides avalanche robustness to the device and over voltage protection to the transistor.

公开(公告)号：US12009791B2

公开(公告)日：2024-06-11

申请号：US17702312

申请日：2022-03-23

Applicant: Analog Devices, Inc.

Inventor： Abhishek Bandyopadhyay

IPC: H03F3/217 ,  H03M3/00 ,  H04R3/02

CPC classification number: H03F3/2175 ,  H03M3/412 ,  H03M3/464 ,  H04R3/02 ,  H03F2200/03 ,  H03F2200/331 ,  H03F2200/351

Abstract: Systems and methods are provided for architectures for a digital class D driver that increase the power efficiency of the class D driver. In particular, systems and methods are provided for a digital class D driver having a feedback analog-to-digital converter (ADC) that can have a latency of 1 cycle or more than 1 cycle. A feedback ADC with a latency of 1 cycle or more is significantly lower power than a low latency feedback ADC. Systems and methods are disclosed for a power efficient digital class D driver architecture that allows for a latency of one or more cycles in the feedback ADC.

公开(公告)号：US12001597B2

公开(公告)日：2024-06-04

申请号：US18327273

申请日：2023-06-01

Applicant: Analog Devices, Inc.

Inventor： Albert Rooyakkers ,  Ken Doucette

IPC: G06F21/86 ,  G06F21/60 ,  G06F21/71 ,  H05K5/02

CPC classification number: G06F21/86 ,  G06F21/604 ,  G06F21/71 ,  H05K5/0208

Abstract: An industrial control system module and methods are described for self-destruction or the destruction and/or erasure of sensitive data within the industrial control system module upon an indication of an unauthorized module access event. In an implementation, a secure industrial control system module includes a circuit board including electrical circuitry; a sealed encasement that houses the circuit board, where the sealed encasement includes a housing having a first housing side and a second housing side, where the housing is configured to house the circuit board when the first housing side and the second housing side are coupled together; and a first sensor component integrated with the sealed encasement, where the first sensor component is communicably coupled to the circuit board and electrical circuitry and is configured to provide an indication of an unauthorized access event.

公开(公告)号：US11981560B2

公开(公告)日：2024-05-14

申请号：US17342442

申请日：2021-06-08

Applicant: Analog Devices, Inc.

Inventor： Xin Zhang ,  Christopher Needham ,  Andrew Proudman ,  Nikolay Pokrovskiy ,  George M. Molnar, II ,  Laura Cornelia Popa ,  Michael Judy

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00325 ,  B81B7/0048 ,  B81C1/00063 ,  B81B2203/01

Abstract: A stress-isolated microelectromechanical systems (MEMS) device and a method of manufacture of the stress-isolated MEMS device are provided. MEMS devices may be sensitive to stress and may provide lower performance when subjected to stress. A stress-isolated MEMS device may be manufactured by etching a trench and/or a cavity in a first side of a substrate and subsequently forming a MEMS device on a surface of a platform opposite the first side of the substrate. Such a stress-isolated MEMS device may exhibit better performance than a MEMS device that is not stress-isolated. Moreover, manufacturing the MEMS device by first forming a trench and cavity on a backside of a wafer, before forming the MEMS device on a suspended platform, provides increased yield and allows for fabrication of smaller parts, in at least some embodiments.

公开(公告)号：US11977622B2

公开(公告)日：2024-05-07

申请号：US17094013

申请日：2020-11-10

Applicant: Analog Devices, Inc.

Inventor： Timothy Clish ,  Samuel Galpin ,  James G. Calvin ,  Albert Rooyakkers

IPC: G06F21/44 ,  H04L9/14 ,  H04L9/30 ,  H04L9/32 ,  H04L9/40 ,  H04L67/12

CPC classification number: G06F21/445 ,  H04L9/14 ,  H04L9/30 ,  H04L9/3263 ,  H04L9/3273 ,  H04L63/08 ,  H04L63/0823 ,  H04L63/164 ,  G06F2212/175 ,  H04L67/12

Abstract: A set of redundant industrial control system communications/control modules includes at least a first communications/control module and a second communications/control module. The first and second communications/control modules are configured to perform an authentication sequence including: transmitting a request datagram from the first communications/control module to the second communications/control module, the request datagram including a first nonce, a first device authentication key certificate, and a first identity attribute certificate; transmitting a response datagram from the second communications/control module to the first communications/control module, the response datagram including a second nonce, a first signature associated with the first and second nonces, a second device authentication key certificate, and a second identity attribute certificate; and transmitting an authentication datagram from the first communications/control module to the second communications/control module when the response datagram is valid, the authentication datagram including a second signature associated with the first and second nonces.