公开(公告)号：US20100025479A1

公开(公告)日：2010-02-04

申请号：US12181401

申请日：2008-07-29

Applicant: Gerald K Bartley ,  Darryl J. Becker ,  Todd A. Christensen ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  John E. Sheets, II

Inventor： Gerald K Bartley ,  Darryl J. Becker ,  Todd A. Christensen ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  John E. Sheets, II

IPC: G06K19/06

CPC classification number: G06F21/87

Abstract: A method and apparatus include conductive material doped within a microchip that accumulates a detectable charge in the presence of ions. Such ions may result from a focused ion beam or other unwelcome technology exploitation effort. Circuitry sensing the charge buildup in the embedded, doped material may initiate a defensive action intended to defeat the tampering operation.

Abstract translation: 一种方法和装置包括掺杂在微芯片内的导电材料，其在离子存在下累积可检测的电荷。 这样的离子可能由聚焦离子束或其他不受欢迎的技术开发而产生。 感测嵌入的掺杂材料中的电荷积累的电路可以启动旨在击败篡改操作的防御动作。

公开(公告)号：US20090305463A1

公开(公告)日：2009-12-10

申请号：US12134728

申请日：2008-06-06

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: H01L21/58

CPC classification number: H01L25/0657 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552

Abstract: A method for thermal optimization comprising the steps of stacking a first chip layer and a second chip layer wherein the second chip layer is rotated in relation to the first chip layer wherein a first hot spot on the first chip layer and a second hot spot on the second chip layer are not spatially aligned; routing a signal input through the first chip layer from a first chip pad on the first chip layer to a first silicon via so as to form a physical input to output twist and a first signal output; and routing the first signal output from the first chip layer through a second chip layer from a second chip pad on the second chip layer to a second silicon via so as to form a second signal output.

Abstract translation: 一种用于热优化的方法，包括以下步骤：堆叠第一芯片层和第二芯片层，其中第二芯片层相对于第一芯片层旋转，其中第一芯片层上的第一热点和第一芯片层上的第二热点 第二芯片层不在空间上对准; 将通过第一芯片层输入的信号从第一芯片层上的第一芯片焊盘传送到第一硅通孔，以便形成物理输入以输出扭曲和第一信号输出; 以及将从第一芯片层输出的第一信号通过第二芯片层从第二芯片层上的第二芯片焊盘路由到第二硅通孔，以形成第二信号输出。

公开(公告)号：US20080276214A1

公开(公告)日：2008-11-06

申请号：US11742970

申请日：2007-05-01

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: G06F17/50

CPC classification number: H01L23/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Connection assignments of differential signals within an integrated circuit (IC) package are automatically made in the design and manufacturing process of the IC package, for use in automated computing systems. Either predefined pairs of pins at both ends or pairs of pins automatically paired or a combination of both are used in the creation of an imaginary pin or midpoint between the pair. Then the point-to-point connections of the pair are automatically detangled. Once the imaginary midpoint-to-midpoint connections are created, the real differential connections can then be assigned.

Abstract translation: 集成电路（IC）封装中的差分信号的连接分配在IC封装的设计和制造过程中自动进行，用于自动化计算系统。 两端的一对预定义的引脚对或两对引脚自动配对或两者的组合用于在该对之间创建假想引脚或中点。 然后，该对的点对点连接将自动错位。 一旦创建了虚拟的中点到中点连接，则可以分配实际的差分连接。

公开(公告)号：US07362651B2

公开(公告)日：2008-04-22

申请号：US11383023

申请日：2006-05-12

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: G11C8/00

CPC classification number: G11C5/063 ,  G11C7/1048 ,  G11C7/1066

Abstract: A double-data-rate two synchronous dynamic random access (DDR2) memory circuit includes a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory core having a common output wherein a high-speed output path and a low-speed output path are coupled together by an output coupling and further coupled to the common output of the memory core.

Abstract translation: 双数据速率两同步动态随机存取（DDR2）存储器电路包括低速输入路径和通过输入耦合耦合到其上的高速输入路径并形成公共输入，公共输入耦合到存储器核心 存储器芯具有公共输出，其中高速输出路径和低速输出路径通过输出耦合耦合在一起并进一步耦合到存储器核心的公共输出端。

公开(公告)号：US07036709B2

公开(公告)日：2006-05-02

申请号：US10703353

申请日：2003-11-07

Applicant: Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew B. Maki ,  Mark Owen Maxson

Inventor： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew B. Maki ,  Mark Owen Maxson

IPC: B23K31/02 ,  B23K35/12 ,  B23K35/14

CPC classification number: H05K3/3436 ,  H05K1/0219 ,  H05K2201/09609 ,  H05K2201/10378 ,  H05K2203/0415 ,  Y02P70/613

Abstract: A method and structure are provided for implementing a column attach coupled noise suppressor for a solder column structure of the type used to join a substrate to a circuit card. The electrical noise suppressor structure includes a plurality of elongated through openings that are arranged in a predefined pattern. The elongated through openings have electrically conductive sidewalls and are electrically connected together. The predefined pattern of the elongated, electrically conductive through openings corresponds to a layout of solder columns. The solder columns are attached at one end to either a substrate or a circuit card and are inserted through the elongated through openings of the electrical noise suppressor structure, spaced apart from the electrically conductive sidewalls. Then the solder columns are attached at the other end to the other one of the substrate or circuit card.

Abstract translation: 提供了一种用于实现用于将基板连接到电路卡的类型的焊料柱结构的列连接耦合噪声抑制器的方法和结构。 电噪声抑制器结构包括以预定图案布置的多个细长通孔。 细长的通孔具有导电侧壁并电连接在一起。 细长的导电通孔的预定图案对应于焊料柱的布局。 焊料柱的一端连接到基板或电路卡，并且通过与导电侧壁间隔开的电噪声抑制器结构的细长通孔插入。 然后，焊料柱在另一端连接到另一个衬底或电路卡。

公开(公告)号：US08214657B2

公开(公告)日：2012-07-03

申请号：US12181387

申请日：2008-07-29

Applicant: Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson ,  John E. Sheets, II

Inventor： Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson ,  John E. Sheets, II

IPC: G06F11/30

CPC classification number: G06F21/755 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

Abstract: A method, program product and apparatus include resistance structures positioned proximate security sensitive microchip circuitry. Alteration in the position, makeup or arrangement of the resistance structures may be detected and initiate an action for defending against a reverse engineering or other exploitation effort. The resistance structures may be automatically and selectively designated for monitoring. Some of the resistance structures may have different resistivities. The sensed resistance may be compared to an expected resistance, ratio or other resistance-related value. The structures may be intermingled with false structures, and may be overlapped or otherwise arranged relative to one another to further complicate unwelcome analysis.

Abstract translation: 一种方法，程序产品和装置包括位于安全敏感的微芯片电路附近的电阻结构。 可以检测抵抗结构的位置，构成或布置的变化，并启动防止逆向工程或其他开发工作的动作。 电阻结构可以自动和选择性地指定用于监测。 一些电阻结构可能具有不同的电阻率。 感测的电阻可以与期望的电阻，比率或其他电阻相关值进行比较。 结构可能与假结构混合，并且可以相对于彼此重叠或以其它方式布置，以进一步使不受欢迎的分析复杂化。

公开(公告)号：US20120146711A1

公开(公告)日：2012-06-14

申请号：US12966303

申请日：2010-12-13

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Philip R. Germann ,  Andrew B. Maki ,  John E. Sheets, II

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Philip R. Germann ,  Andrew B. Maki ,  John E. Sheets, II

IPC: G11C5/14 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/823431 ,  H01L21/823437 ,  H01L23/481 ,  H01L29/785 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2924/014

Abstract: A semiconductor chip has a gated through silicon via (TSVG). The TSVG may be switched so that the TSVG can be made conducting or non-conducting. The semiconductor chip may be used between a lower level semiconductor chip and a higher semiconductor chip to control whether a voltage supply on the lower level semiconductor chip is connected to or disconnected from a voltage domain in the upper level semiconductor chip. The TSVG comprises an FET controlled by the lower level chip as a switch.

Abstract translation: 半导体芯片具有选通硅通孔（TSVG）。 可以切换TSVG，使得TSVG可以导通或不导通。 半导体芯片可以在下位半导体芯片和较高半导体芯片之间使用，以控制下位半导体芯片上的电压供应是连接到上级半导体芯片中的电压域还是与其断开。 TSVG包括由下级芯片作为开关控制的FET。

公开(公告)号：US07838336B2

公开(公告)日：2010-11-23

申请号：US11860226

申请日：2007-09-24

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: H01L21/98

CPC classification number: H01L21/563 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81365 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2924/0001 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2224/13099

Abstract: A method of making an integrated circuit package includes forming a through hole in an integrated circuit and assembling a die containing the integrated circuit on a carrier so that the die is mechanically and electrically connected to the carrier. Thereafter, an underfill material is dispensed between the die and the carrier via the through hole.

Abstract translation: 制造集成电路封装的方法包括在集成电路中形成通孔并将包含集成电路的管芯组装在载体上，使得管芯机械地和电连接到载体上。 此后，通过通孔将底部填充材料分配在模具和载体之间。

公开(公告)号：US20100031376A1

公开(公告)日：2010-02-04

申请号：US12181357

申请日：2008-07-29

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  Carl-Otto Nilsen

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  Carl-Otto Nilsen

IPC: G06F21/02

CPC classification number: G06F21/87

Abstract: Apparatus, method and program product detect an attempt to tamper with a microchip by determining that an electrical path comprising one or more connections and a metal plate attached to the backside of a microchip has become disconnected or otherwise altered. A tampering attempt may also be detected in response to the presence of an electrical path that should not be present, as may result from the microchip being incorrectly reconstituted. Actual and/or deceptive paths may be automatically selected and monitored to further confound a reverse engineering attempt.

Abstract translation: 装置，方法和程序产品通过确定包括一个或多个连接的电路径和连接到微芯片的背面的金属板已经断开或以其他方式改变来检测试图篡改微芯片。 响应于不可能存在的电路径的存在，也可以检测到篡改尝试，这可能是因为微芯片被错误地重新构成。 可以自动选择和监视实际和/或欺骗性路径，以进一步混淆反向工程尝试。

公开(公告)号：US20100026313A1

公开(公告)日：2010-02-04

申请号：US12181365

申请日：2008-07-29

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: G01R31/12 ,  G01R27/26

CPC classification number: H01L23/576 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/3011 ,  H01L2224/0401

Abstract: Apparatus, method and program product may detect an attempt to tamper with a microchip by detecting an unacceptable alteration in a measured capacitance associated with capacitance structures proximate the backside of a microchip. The capacitance structures typically comprise metallic shapes and may connect using through-silicon vias to active sensing circuitry within the microchip. In response to the sensed change, a shutdown, spoofing, self-destruct or other defensive action may be initiated to protect security sensitive circuitry of the microchip.

Abstract translation: 装置，方法和程序产品可以通过检测与微芯片的背面附近的电容结构相关联的测量电容中的不可接受的改变来检测试图篡改微芯片。 电容结构通常包括金属形状，并且可以使用硅硅通孔连接到微芯片内的主动感测电路。 响应于感测到的变化，可以启动关机，欺骗，自毁或其他防御动作以保护微芯片的安全敏感电路。