Hierarchical transmission in wireless communications

    公开(公告)号:US09906964B2

    公开(公告)日:2018-02-27

    申请号:US14510510

    申请日:2014-10-09

    CPC classification number: H04W24/02 H04L5/00 H04L5/0037 H04L5/0046 H04L27/3488

    Abstract: A wireless communication device includes a communication interface and a processor that operate to generate a first transmission stream by processing first information based on first parameter(s) and a second transmission stream by processing second information based on second parameter(s). In some examples, the second at least one parameter is relatively less robust than the first at least one parameter, and the second information augments the first information when combined with the first information. The wireless communication device then transmits the first transmission stream and the second transmission stream to at least one other wireless communication device. Examples of such parameters include forward error correction (FEC) code, error correction code (ECC), modulation coding set (MCS), modulation type including a mapping of constellation points arranged in a constellation, power (e.g., transmit (TX) power), orthogonal frequency division multiplexing (OFDM) configuration, and/or a multiple-input-multiple-output (MIMO) configuration.

    Multi-chip module with a high-rate interface

    公开(公告)号:US09843538B2

    公开(公告)日:2017-12-12

    申请号:US14599411

    申请日:2015-01-16

    CPC classification number: H04L49/30 H04J3/047 H04J3/0697 H04L45/745 H04L49/40

    Abstract: A multi-chip module (MCM) may include a substrate, and first and second physical-layer (PHY) chips mounted on the substrate. In some implementations, the first PHY chip includes a multiplexer and a PHY circuit. The multiplexer is configured to receive a multiplexed data stream from a media access control (MAC) device, to demultiplex the multiplexed data stream into first and second data streams, to output the first data stream to the PHY circuit, and to output the second data stream to the second PHY chip. In some implementations, the first PHY includes a router and a PHY circuit. The router is configured to receive a plurality of data packets from a MAC device, to route one or more of the data packets having a first address to the PHY circuit, and to route one or more of the data packets having a second address to the second PHY chip.

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