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公开(公告)号：US20210183779A1
公开(公告)日：2021-06-17
申请号：US17024182
申请日：2020-09-17
IPC分类号： H01L23/538 , H01L23/00 , H01L21/50
摘要： Disclosed embodiments include multi-level fan-out integrated-circuit package substrates that provide a low-loss path to active and passive devices, by shunting away from interconnects and inductive loops. The multi-level form factor of a molded mass, allows for the low-loss path.
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公开(公告)号：US10943792B2
公开(公告)日：2021-03-09
申请号：US16325665
申请日：2016-09-27
IPC分类号： H01L25/00 , H01L21/48 , H01L23/48 , H01L23/538 , H01L23/552 , H01L25/065 , H01L29/06 , H01L23/00 , H01L25/18
摘要： A system in package device includes a landed first die disposed on a package substrate. The landed first die includes a notch that is contoured and that opens the backside surface of the die to a ledge. A stacked die is mounted at the ledge and the two dice are each contacted by a through-silicon via (TSV). The system in package device also includes a landed subsequent die on the package substrate and a contoured notch in the landed subsequent die and the notch in the first die form a composite contoured recess into which the stacked die is seated.
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公开(公告)号：US20210066185A1
公开(公告)日：2021-03-04
申请号：US16912619
申请日：2020-06-25
IPC分类号： H01L23/522 , H01L21/768 , H01L23/528
摘要： Disclosed embodiments include frame-array interconnects that have a ledge portion to accommodate a passive device. A seated passive device is between at least two frame-array interconnects for semiconductor package-integrated decoupling capacitors.
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公开(公告)号：US20200083170A1
公开(公告)日：2020-03-12
申请号：US16451530
申请日：2019-06-25
IPC分类号： H01L23/538 , H01L25/16 , H01L21/48 , H01L25/00
摘要： A semiconductor device and associated methods are disclosed. In one example, dies are interconnected through a bridge in a substrate. A reference voltage stack extends over at least a portion of the interconnect bridge, and a passive component is coupled to the reference voltage stack. In one example, the passive component helps to reduce interference in the power supply to components in the semiconductor device, such as the dies and the interconnect bridge.
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25.发明申请公开(公告)号：US20190181126A1
公开(公告)日：2019-06-13
申请号：US16019023
申请日：2018-06-26
IPC分类号： H01L25/16 , H01L23/498 , H01L25/00 , H01L23/00 , H01Q21/22 , H01Q1/52 , H01Q21/00 , H01Q1/22
摘要： A system-in-package includes a package substrate that at least partially surrounds an embedded radio-frequency integrated circuit chip and a processor chip mated to a redistribution layer. A wide-band phased-array antenna module is mated to the package substrate with direct interconnects from the radio-frequency integrated circuit chip to antenna patches within the antenna module. Additionally, fan-out antenna pads are also coupled to the radio-frequency integrated circuit chip.
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26.发明申请MULTI-DIE SEMICONDUCTOR STRUCTURE WITH INTERMEDIATE VERTICAL SIDE CHIP AND SEMICONDUCTOR PACKAGE FOR SAME 审中-公开具有中间垂直侧芯片和半导体封装的多模半导体结构公开(公告)号：US20170018530A1
公开(公告)日：2017-01-19
申请号：US15278532
申请日：2016-09-28
IPC分类号： H01L25/065 , H01L23/00 , H01L23/538
CPC分类号： H01L25/0652 , H01L23/3128 , H01L23/3142 , H01L23/481 , H01L23/5386 , H01L23/5389 , H01L24/02 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/02371 , H01L2224/02372 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/06182 , H01L2224/06183 , H01L2224/06189 , H01L2224/06517 , H01L2224/131 , H01L2224/16137 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/17181 , H01L2224/17183 , H01L2224/32225 , H01L2224/73204 , H01L2224/80894 , H01L2224/81815 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06565 , H01L2924/00014 , H01L2924/10253 , H01L2924/12042 , H01L2924/1432 , H01L2924/1434 , H01L2924/1461 , H01L2924/15311 , H01L2924/15787 , H01L2924/18161 , H01L2924/351 , H01L2924/00012 , H01L2224/80 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.
摘要翻译： 描述了具有中间垂直侧芯片的半导体多管芯结构以及容纳这种半导体多管芯结构的封装。 在一个示例中，多管芯半导体结构包括具有半导体管芯的第一基本水平布置的第一主堆叠管芯（MSD）结构。 还包括具有半导体管芯的第二基本水平布置的第二MSD结构。 中间垂直侧芯片（i-VSC）设置在电耦合到第一和第二MSD结构之间。
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公开(公告)号：US20150277506A1
公开(公告)日：2015-10-01
申请号：US14229835
申请日：2014-03-29
IPC分类号： G06F1/16
摘要： Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low profile hinge design that includes a micro-hinge. The micro-hinge can couple a first element to a second element and can include a first attachment that couples to the first element, a second attachment that couples to the second element, and a plurality of linkages that couples the first attachment to the second attachment. The low profile hinge can further include a plurality of micro-hinges and a plurality of support rods.
摘要翻译： 本文描述的特定实施例提供了一种诸如笔记本计算机或笔记本电脑的电子设备，其包括耦合到多个电子部件（其包括任何类型的部件，元件，电路等）的电路板。 电子设备的一个具体实施例可以包括包括微铰链的低轮廓铰链设计。 微铰链可以将第一元件耦合到第二元件并且可以包括耦合到第一元件的第一连接件，耦合到第二元件的第二连接件和将第一附件耦合到第二附件的多个连接件 。 小型铰链还可以包括多个微铰链和多个支撑杆。
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公开(公告)号：US20140291866A1
公开(公告)日：2014-10-02
申请号：US13852876
申请日：2013-03-28
申请人： Toong Erh Ooi , Bok Eng Cheah , Nitesh Nimkar
发明人： Toong Erh Ooi , Bok Eng Cheah , Nitesh Nimkar
IPC分类号： H01L23/498 , H01L23/00
CPC分类号： H01L24/82 , H01L21/4846 , H01L21/4857 , H01L21/486 , H01L23/498 , H01L23/49822 , H01L23/49827 , H01L23/50 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/73 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/82005 , H01L2224/82039 , H01L2224/821 , H01L2224/82345 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1058 , H01L2225/1076 , H01L2924/12042 , H01L2924/1517 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/18162 , H05K1/185 , H05K3/4682 , H05K2201/10674 , H01L2924/00012 , H01L2924/00
摘要： An apparatus including a die; and a build-up carrier including alternating layers of conductive material and dielectric material disposed on a device side of the die and dielectric material embedding a portion of a thickness dimension of the die; and a plurality of carrier contact points disposed at a gradation between the device side of the die and the embedded thickness dimension of the die and configured for connecting the carrier to a substrate. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; forming a build-up carrier adjacent a device side of a die, wherein the build-up carrier includes a dielectric material defining a gradation between the device side of the die and a backside of the die, the gradation including a plurality of carrier contact points; and separating the die and the carrier from the sacrificial substrate.
摘要翻译： 一种包括模具的设备; 以及堆叠载体，其包括设置在所述管芯的器件侧上的交替的导电材料层和介电材料层，以及包埋所述管芯的厚度尺寸的一部分的电介质材料; 以及多个载体接触点，其设置在所述管芯的器件侧和所述管芯的嵌入的厚度尺寸之间的灰度处，并且被配置为将所述载体连接到衬底。 一种方法，包括在牺牲衬底上设置管芯，其中模具的器件侧与牺牲衬底相对; 在模具的器件侧附近形成堆积载体，其中所述积聚载体包括在所述管芯的器件侧和所述管芯的背面之间限定灰度的介电材料，所述等级包括多个载体接触点 ; 以及将所述管芯和所述载体与所述牺牲衬底分离。
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29.发明授权公开(公告)号：US08198716B2
公开(公告)日：2012-06-12
申请号：US11728534
申请日：2007-03-26
IPC分类号： H01L23/48
CPC分类号： H01L25/18 , H01L24/73 , H01L25/0657 , H01L2224/32145 , H01L2224/48145 , H01L2224/48227 , H01L2224/48465 , H01L2224/73257 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/14 , H01L2924/351 , H01L2924/00 , H01L2924/00012
摘要： Methods and apparatus to provide die backside connections are described. In one embodiment, the backside of a die is metallized and coupled to another die or a substrate. Other embodiments are also described.
摘要翻译： 描述提供模背侧连接的方法和装置。 在一个实施例中，管芯的背面被金属化并且耦合到另一个管芯或衬底。 还描述了其它实施例。
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公开(公告)号：US20120003792A1
公开(公告)日：2012-01-05
申请号：US13231953
申请日：2011-09-13
IPC分类号： H01L21/50
CPC分类号： H01L25/0657 , H01L23/481 , H01L24/16 , H01L24/31 , H01L25/18 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/83894 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/00
摘要： The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed.
摘要翻译： 描述了电子组件的形成。 一个实施例包括每个包括前侧和后侧的第一和第二半导体管芯结构，前侧包括有源区，背面包括金属区和非金属区。 第一和第二半导体管芯结构包括多个通孔，通孔在有源区和背侧金属区之间形成电连接。 第一和第二半导体管芯结构与第一半导体管芯结构的背侧上的金属区域中的至少一个与第二半导体管芯结构的背面上的金属区域中的至少一个直接接触而堆叠在一起。 描述和要求保护其他实施例。
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