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    Prefetch Circuit for Cache Memory
    21.
    发明公开
    Prefetch Circuit for Cache Memory 审中-公开

    公开(公告)号：US20230350806A1

    公开(公告)日：2023-11-02

    申请号：US17661394

    申请日：2022-04-29

    Applicant: Cadence Design Systems, Inc.

    Inventor： Avishai Tvila

    IPC: G06F12/0862

    CPC classification number: G06F12/0862 ,  G06F2212/602

    Abstract: A prefetch circuit coupled to a cache memory circuit includes a storage circuit that stores multiple virtual-to-physical address map entries. In response to receiving an indication of a miss for an access request to the cache memory circuit, the prefetch circuit generates a prefetch address and compares it to a demand address included in the access request. In response to determining that the demand address and the prefetch address are in different memory pages, the prefetch circuit generates a prefetch request using physical page information retrieved from the storage circuit.

    Technique for Overriding Memory Attributes
    22.
    发明公开
    Technique for Overriding Memory Attributes 审中-公开

    公开(公告)号：US20230350805A1

    公开(公告)日：2023-11-02

    申请号：US17661427

    申请日：2022-04-29

    Applicant: Cadence Design Systems, Inc.

    Inventor： Robert T. Golla ,  Thomas M. Wicki

    IPC: G06F12/0837 ,  G06F12/0877 ,  G06F9/30

    CPC classification number: G06F12/0837 ,  G06F12/0877 ,  G06F9/30138

    Abstract: Techniques are disclosed relating to an apparatus that includes a plurality of memory access control registers that are programmable with respective address ranges within an address space. The apparatus further includes a memory access circuit configured to receive a command for performing a memory access, the command specifying an address corresponding to a location in a memory circuit. In response to the address being located within an address range of a particular one of the plurality of memory access control registers, the memory access circuit is configured to perform the command using override memory parameters that have been programmed into the particular memory access control register instead of a default set of attributes for the address space.

    Managing Multiple Cache Memory Circuit Operations
    23.
    发明公开
    Managing Multiple Cache Memory Circuit Operations 审中-公开

    公开(公告)号：US20230342296A1

    公开(公告)日：2023-10-26

    申请号：US17660775

    申请日：2022-04-26

    Applicant: Cadence Design Systems, Inc.

    Inventor： Robert T. Golla ,  Matthew B. Smittle

    IPC: G06F12/0811

    CPC classification number: G06F12/0811 ,  G06F2212/62

    Abstract: A cache memory circuit capable of dealing with multiple conflicting requests to a given cache line is disclosed. In response to receiving an acquire request for the given cache line from a particular lower-level cache memory circuit, the cache memory circuit sends probe requests regarding the given cache line to other lower-level cache memory circuits. In situations where a different lower-level cache memory circuit is simultaneously trying to evict the given cache line at the particular lower-level cache memory circuit is trying to obtain a copy of the cache line, the cache memory circuit performs a series of operations to service both requests and ensure that the particular lower-level cache memory circuit receives a copy of the given cache line that includes any changes in the evicted copy of the given cache line.

    System and method for glitch power estimation
    26.
    发明授权
    System and method for glitch power estimation 有权

    公开(公告)号：US11748534B1

    公开(公告)日：2023-09-05

    申请号：US17572836

    申请日：2022-01-11

    Applicant: Cadence Design Systems, Inc.

    Inventor： Steev Wilcox ,  Daniel Fernandes

    IPC: G06F30/323 ,  G06F111/20 ,  G06F111/08 ,  G06F119/06

    CPC classification number: G06F30/323 ,  G06F2111/08 ,  G06F2111/20 ,  G06F2119/06

    Abstract: Embodiments include herein are directed towards a system and method for estimating glitch power associated with an emulation process is provided. Embodiments may include accessing, using a processor, information associated with an electronic design database and generating cycle accurate waveform information at each node of a netlist based upon, at least in part, a portion of the electronic design database. Embodiments may further include generating a probability-based model for a plurality of inputs associated with the netlist and determining one or more partial glitch transitions from each probability-based model. Embodiments may also include combining the one or more partial glitch transitions with the cycle accurate waveform information to obtain a glitch power estimation.

    Device and method for low-latency and encrypted hardware layer communication
    28.
    发明授权
    Device and method for low-latency and encrypted hardware layer communication 有权

    公开(公告)号：US11722291B1

    公开(公告)日：2023-08-08

    申请号：US17399953

    申请日：2021-08-11

    Applicant: CADENCE DESIGN SYSTEMS, INC.

    Inventor： Steven Ho ,  Gopi Krishnamurthy ,  Anish Mathew

    IPC: H04L9/06 ,  H04L9/08

    CPC classification number: H04L9/0618 ,  H04L9/065 ,  H04L9/0816 ,  H04L9/0869

    Abstract: A method of low-latency and encrypted hardware layer communication includes calculating, by an encryption circuit of a communication bridge controller, a pre-calculated encryption keys corresponding to a block encryptor of the encryption circuit, each block encryptor configured to use a corresponding pre-calculated encryption key to encrypt a corresponding unencrypted data block of a data transmission having one or more unencrypted data blocks, storing the one or more pre-calculated encryption keys in an encryption key memory associated with the communication bridge, for each unecrypted data block, encrypting the unencrypted data block using the corresponding pre-calculated encryption key to generate an encrypted data block and an authentication code block for the unencrypted data block, aggregating one or more encrypted data blocks into an encrypted data transmission, and generating an authenticated code corresponding to the encrypted data transmission based upon each of the authentication code blocks of each of the encrypted data blocks.

    Method, product, and apparatus for a machine learning process leveraging input sparsity on a pixel by pixel basis
    30.
    发明授权
    Method, product, and apparatus for a machine learning process leveraging input sparsity on a pixel by pixel basis 有权

    公开(公告)号：US11676068B1

    公开(公告)日：2023-06-13

    申请号：US16946673

    申请日：2020-06-30

    Applicant: Cadence Design Systems, Inc.

    Inventor： Michael Patrick Zimmer ,  Ngai Ngai William Hung ,  Yong Liu ,  Dhiraj Goswami

    IPC: G06N20/00 ,  G06F17/16

    CPC classification number: G06N20/00 ,  G06F17/16

    Abstract: An approach includes a method, product, and apparatus for dynamically removing sparse data on a pixel by pixel basis. In some embodiments, a machine learning processing job is received. The machine learning processing job is then executed on a pixel by pixel basis by selecting non-zero data values for input into a systolic array, wherein sparse data is not selected for input into the systolic array. Subsequently, a message is generated that provides an indication of whether the execution completed successfully. In some embodiments, the machine learning processing job comprises at least a plurality of multiply and accumulate operations. In some embodiments, at least one data value equal to zero for the machine learning processing job is not input into a systolic array. In some embodiments, a plurality of weights are input into a plurality of columns for each cycle.

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