公开(公告)号：US20060017136A1

公开(公告)日：2006-01-26

申请号：US11173624

申请日：2005-07-01

Applicant: Seok-jun Won ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

Inventor： Seok-jun Won ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

IPC: H01L29/00

CPC classification number: H01L28/40 ,  H01L28/65 ,  Y10S438/957

Abstract: In a capacitor of an analog semiconductor device having a multi-layer dielectric film and a method of manufacturing the same, the multi-layer dielectric film can be readily manufactured, has weak reactivity with corresponding electrodes and offers excellent leakage current characteristics. In order to obtain these advantages, a lower dielectric film having a negative quadratic VCC, an intermediate dielectric film having a positive quadratic VCC, and an upper dielectric film having a negative quadratic VCC are sequentially formed between a lower electrode and an upper electrode. The lower dielectric film and the upper dielectric film may be composed of SiO2. The intermediate dielectric film may be composed of HFO2.

Abstract translation: 在具有多层电介质膜的模拟半导体器件的电容器及其制造方法中，可以容易地制造多层电介质膜，与相应的电极具有弱反应性并提供优异的漏电流特性。 为了获得这些优点，在​​下电极和上电极之间顺序地形成具有负二次VCC的下电介质膜，具有正二次VCC的中间电介质膜和具有负二次VCC的上电介质膜。 下电介质膜和上电介质膜可以由SiO 2组成。 中间电介质膜可以由HFO 2 N 2构成。

公开(公告)号：US20050196915A1

公开(公告)日：2005-09-08

申请号：US11063942

申请日：2005-02-23

Applicant: Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon

Inventor： Yong-Kuk Jeong ,  Seok-Jun Won ,  Dae-Jin Kwon

IPC: H01L27/10 ,  H01L21/00 ,  H01L21/20 ,  H01L21/8234

CPC classification number: H01L28/40 ,  H01L21/02183 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/3211

Abstract: There is provided a method of fabricating an analog capacitor using a post-treatment technique. The method includes forming a lower insulating layer on a semiconductor substrate. A bottom electrode is formed on the lower insulating layer, and a capacitor dielectric layer is formed on the bottom electrode. Then, the capacitor dielectric layer is post-treated in a deoxidizing medium. Then, the post-treated capacitor dielectric layer is post-treated in an oxidizing medium. A top electrode is formed on the post-treated capacitor dielectric layer. The analog capacitor fabricated through the post-treatment as above has a low VCC.

Abstract translation: 提供了使用后处理技术制造模拟电容器的方法。 该方法包括在半导体衬底上形成下绝缘层。 底电极形成在下绝缘层上，电容器电介质层形成在底电极上。 然后，将电容器电介质层在脱氧介质中进行后处理。 然后，将后处理电容器电介质层在氧化介质中进行后处理。 顶部电极形成在后处理电容器介电层上。 通过如上所述的后处理制造的模拟电容具有低VCC。

公开(公告)号：US20050087879A1

公开(公告)日：2005-04-28

申请号：US10969098

申请日：2004-10-20

Applicant: Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

Inventor： Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

IPC: H01L27/10 ,  H01L21/02 ,  H01L21/768 ,  H01L23/48 ,  H01L27/08

CPC classification number: H01L28/91 ,  H01L21/76807 ,  H01L21/76838 ,  H01L27/0805

Abstract: A logic device having a vertically extending MIM capacitor between interconnect layers includes a semiconductor substrate. A lower interconnect layer is located over the semiconductor substrate, and an upper interconnect layer is located over the lower interconnect layer. A U-shaped lower metal plate is interposed between the lower interconnect layer and the upper interconnect layer. The U-shaped lower metal plate directly contacts the lower interconnect layer. The capacitor dielectric layer covers the inner surface of the lower metal plate. Further, the capacitor dielectric layer has an extension portion interposed between the brim of the lower metal plate and the upper interconnect layer. An upper metal plate covers the inner surface of the capacitor dielectric layer. The upper metal plate is in contact with the upper interconnect layer and is confined by the capacitor dielectric layer.

Abstract translation: 在互连层之间具有垂直延伸的MIM电容器的逻辑器件包括半导体衬底。 下部互连层位于半导体衬底上方，并且上互连层位于下互连层上。 U形下金属板插入在下互连层和上互连层之间。 U形下金属板直接接触下互连层。 电容器电介质层覆盖下金属板的内表面。 此外，电容器介电层具有插入在下金属板的边缘和上互连层之间的延伸部分。 上金属板覆盖电容器介电层的内表面。 上金属板与上互连层接触并被电容器电介质层约束。

公开(公告)号：US20050003089A1

公开(公告)日：2005-01-06

申请号：US10859166

申请日：2004-06-03

Applicant: Seok-Jun Won ,  Dae-Jin Kwon ,  Yong-Kuk Jeong

Inventor： Seok-Jun Won ,  Dae-Jin Kwon ,  Yong-Kuk Jeong

IPC: C23C16/00 ,  C23C16/02 ,  C23C16/26 ,  C23C16/44 ,  C23C16/455 ,  C30B29/02 ,  C30B29/60

CPC classification number: C23C16/4554 ,  C23C16/0281 ,  C23C16/26 ,  C30B29/02 ,  C30B29/605

Abstract: A method of forming a carbon nano-material layer may involve a cyclic deposition technique. In the method, a chemisorption layer or a chemical vapor deposition layer may be formed on a substrate. Impurities may be removed from the chemisorption layer or the chemical vapor deposition layer to form a carbon atoms layer on the substrate. More than one carbon atoms layer may be formed by repeating the method.

Abstract translation: 形成碳纳米材料层的方法可以包括循环沉积技术。 在该方法中，可以在基板上形成化学吸附层或化学气相沉积层。 杂质可以从化学吸附层或化学气相沉积层去除，以在基底上形成碳原子层。 可以通过重复该方法形成多于一个的碳原子层。

公开(公告)号：US06835621B2

公开(公告)日：2004-12-28

申请号：US10455676

申请日：2003-06-05

Applicant: Jae-yoon Yoo ,  Moon-han Park ,  Dae-jin Kwon

Inventor： Jae-yoon Yoo ,  Moon-han Park ,  Dae-jin Kwon

IPC: H01L218247

CPC classification number: H01L27/11568 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02326 ,  H01L21/28282 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/32105 ,  H01L27/115 ,  H01L29/66833

Abstract: In a method of fabricating a non-volatile memory device with a silicon-oxide-nitride-oxide-silicon (SONOS) structure, a silicon nitride layer, which is a charge trapping layer, and a polysilicon layer, which is a control gate electrode, are electrically isolated from one another in the resulting structure. According to the method, a silicon oxide layer as a tunneling layer and a silicon nitride layer pattern as a charge trapping layer are formed on a semiconductor substrate; an oxidation process is performed to form a silicon nitride oxide layer, as a blocking layer, at top and sides of the silicon nitride layer pattern and to form a gate insulating layer at an exposed portion of the semiconductor substrate; and a control gate electrode is formed on the silicon nitride oxide layer and the gate insulating layer.

Abstract translation: 在制造具有氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）结构的非易失性存储器件的方法中，作为电荷俘获层的氮化硅层和作为控制栅电极的多晶硅层 在所得结构中彼此电隔离。 根据该方法，在半导体衬底上形成作为隧穿层的氧化硅层和作为电荷俘获层的氮化硅层图案; 进行氧化处理以在氮化硅层图案的顶部和侧面形成氮化硅氧化物层作为阻挡层，并在半导体衬底的暴露部分形成栅极绝缘层; 并且在氮氧化硅层和栅极绝缘层上形成控制栅电极。

公开(公告)号：US20170148505A1

公开(公告)日：2017-05-25

申请号：US14946258

申请日：2015-11-19

Applicant: DAE-JIN KWON ,  Kang-Ill Seo

Inventor： DAE-JIN KWON ,  Kang-Ill Seo

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

Abstract: Provided are a semiconductor device. The semiconductor device includes an SRAM cell including a first pull-up transistor, a first pull-down transistor and a first pass transistor formed on a substrate, a first read buffer transistor connected to gate terminals of the first pull-up transistor and the first pull-down transistor, and a second read buffer transistor which shares a drain terminal with the first read buffer transistor, wherein the first read buffer transistor includes a first channel pattern extending in a first direction vertical to an upper surface of the substrate, a first gate electrode which covers a part of the first channel pattern, and a first drain pattern which does not contact the first gate electrode, and which extends in the first direction, and which is electrically connected to the first channel pattern.

公开(公告)号：US07833580B2

公开(公告)日：2010-11-16

申请号：US10859166

申请日：2004-06-03

Applicant: Seok-Jun Won ,  Dae-Jin Kwon ,  Yong-Kuk Jeong

Inventor： Seok-Jun Won ,  Dae-Jin Kwon ,  Yong-Kuk Jeong

IPC: C23C18/00 ,  C23C16/26

CPC classification number: C23C16/4554 ,  C23C16/0281 ,  C23C16/26 ,  C30B29/02 ,  C30B29/605

Abstract: A method of forming a carbon nano-material layer may involve a cyclic deposition technique. In the method, a chemisorption layer or a chemical vapor deposition layer may be formed on a substrate. Impurities may be removed from the chemisorption layer or the chemical vapor deposition layer to form a carbon atoms layer on the substrate. More than one carbon atoms layer may be formed by repeating the method.

Abstract translation: 形成碳纳米材料层的方法可以包括循环沉积技术。 在该方法中，可以在基板上形成化学吸附层或化学气相沉积层。 杂质可以从化学吸附层或化学气相沉积层去除，以在基底上形成碳原子层。 可以通过重复该方法形成多于一个的碳原子层。

公开(公告)号：US07615783B2

公开(公告)日：2009-11-10

申请号：US11436073

申请日：2006-05-17

Applicant: Joon-Hoo Choi ,  Wan-Shick Hong ,  Dae-Jin Kwon ,  Kwan-Wook Jung ,  Sang-Gab Kim ,  Kyu-Ha Jung

Inventor： Joon-Hoo Choi ,  Wan-Shick Hong ,  Dae-Jin Kwon ,  Kwan-Wook Jung ,  Sang-Gab Kim ,  Kyu-Ha Jung

IPC: H01L51/30

CPC classification number: H01L29/66765 ,  G02F1/136227 ,  G02F2001/133357 ,  G02F2001/136236 ,  H01L27/12 ,  H01L29/458 ,  H01L29/4908

Abstract: A thin film transistor array substrate is provided. The substrate includes an insulating substrate, a first signal line formed on the insulating substrate, a first insulating layer formed on the first signal line, a second signal line formed on the first insulating layer while crossing over the first signal line, a thin film transistor connected to the first and the second signal lines, a second insulating layer formed on the thin film transistor, the second insulating layer having dielectric constant about 4.0 or less, and the second insulating layer having a first contact hole exposing a predetermined electrode of the thin film transistor, and a first pixel electrode formed on the second insulating layer while being connected to the predetermined electrode of the thin film transistor through the first contact hole.

公开(公告)号：US07476922B2

公开(公告)日：2009-01-13

申请号：US10969098

申请日：2004-10-20

Applicant: Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

Inventor： Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L28/91 ,  H01L21/76807 ,  H01L21/76838 ,  H01L27/0805

Abstract: A logic device having a vertically extending MIM capacitor between interconnect layers includes a semiconductor substrate. A lower interconnect layer is located over the semiconductor substrate, and an upper interconnect layer is located over the lower interconnect layer. A U-shaped lower metal plate is interposed between the lower interconnect layer and the upper interconnect layer. The U-shaped lower metal plate directly contacts the lower interconnect layer. The capacitor dielectric layer covers the inner surface of the lower metal plate. Further, the capacitor dielectric layer has an extension portion interposed between the brim of the lower metal plate and the upper interconnect layer. An upper metal plate covers the inner surface of the capacitor dielectric layer. The upper metal plate is in contact with the upper interconnect layer and is confined by the capacitor dielectric layer.

Abstract translation: 在互连层之间具有垂直延伸的MIM电容器的逻辑器件包括半导体衬底。 下部互连层位于半导体衬底上方，并且上互连层位于下互连层上。 U形下金属板插入在下互连层和上互连层之间。 U形下金属板直接接触下互连层。 电容器电介质层覆盖下金属板的内表面。 此外，电容器介电层具有插入在下金属板的边缘和上互连层之间的延伸部分。 上金属板覆盖电容器介电层的内表面。 上金属板与上互连层接触并被电容器电介质层约束。

公开(公告)号：US07232492B2

公开(公告)日：2007-06-19

申请号：US11007884

申请日：2004-12-09

Applicant: Seok-Jun Won ,  Weon-Hong Kim ,  Dae-Jin Kwon

Inventor： Seok-Jun Won ,  Weon-Hong Kim ,  Dae-Jin Kwon

IPC: B08B3/12 ,  B08B6/00 ,  B08B7/00

CPC classification number: C23C16/4404 ,  C23C16/4405 ,  H01L21/3141 ,  H01L21/31637

Abstract: There is provided a method of forming a thin film for providing improved fabrication productivity. The method includes introducing a semiconductor substrate into a process chamber. A process thin film is formed on the semiconductor substrate, in which a chamber coating layer is formed on inner walls of the process chamber while the process thin film is formed. The semiconductor substrate is removed from the process chamber. A stress relief layer is formed on the chamber coating layer. After all of the above operations are repeatedly performed at least one time, an in-situ cleaning is performed on the chamber coating layer and the stress relief layer, which are alternately formed in stack on the inner walls of the process chamber.

Abstract translation: 提供了形成薄膜以提高制造生产率的方法。 该方法包括将半导体衬底引入到处理室中。 在半导体衬底上形成工艺薄膜，其中在形成工艺薄膜的同时，在处理室的内壁上形成腔室涂层。 将半导体衬底从处理室中取出。 在室涂层上形成应力消除层。 在上述操作全部反复进行至少一次之后，对处理室内壁交替形成的室涂层和应力消除层进行原位清洗。