公开(公告)号：US20110241128A1

公开(公告)日：2011-10-06

申请号：US12751926

申请日：2010-03-31

申请人： David L. O'Meara ,  Anthony Dip ,  Aelan Mosden ,  Pao-Hwa Chou ,  Richard A. Conti

发明人： David L. O'Meara ,  Anthony Dip ,  Aelan Mosden ,  Pao-Hwa Chou ,  Richard A. Conti

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28247 ,  H01L29/6656

摘要： A semiconducting device with a multilayer sidewall spacer and method of forming are described. In one embodiment, the method includes providing a substrate containing a patterned structure on a surface of the substrate and depositing a first spacer layer over the patterned structure at a first substrate temperature, where the first spacer layer contains a first material. The method further includes depositing a second spacer layer over the patterned substrate at a second substrate temperature that is different from the first substrate temperature, where the first and second materials contain the same chemical elements, and the depositing steps are performed in any order. The first and second spacer layers are then etched to form the multilayer sidewall spacer on the patterned structure.

摘要翻译： 描述了具有多层侧壁间隔件和形成方法的半导体器件。 在一个实施例中，该方法包括在衬底的表面上提供含有图案化结构的衬底，并且在第一衬底温度下在第一衬底温度下沉积在图案化结构上的第一间隔层，其中第一间隔层包含第一材料。 该方法还包括在不同于第一衬底温度的第二衬底温度下在图案化衬底上沉积第二间隔层，其中第一和第二材料含有相同的化学元素，并且沉积步骤以任何顺序进行。 然后蚀刻第一和第二间隔层以在图案化结构上形成多层侧壁间隔物。

公开(公告)号：US07479454B2

公开(公告)日：2009-01-20

申请号：US10674703

申请日：2003-09-30

申请人： David L. O'Meara ,  Daniel Craig Burdett ,  Stephen H. Cabral ,  Gert Leusink ,  John William Kostenko ,  Cory Wajda

发明人： David L. O'Meara ,  Daniel Craig Burdett ,  Stephen H. Cabral ,  Gert Leusink ,  John William Kostenko ,  Cory Wajda

IPC分类号： H01L21/302

CPC分类号： H01L21/67276 ,  B81C99/0065 ,  B81C2201/0138 ,  H01L21/67253

摘要： A method and system for monitoring status of a system component during a process. The method includes exposing a system component to a reactant gas during a process, where the reactant gas is capable of etching the system component material to form an erosion product, and monitoring release of the erosion product during the process to determine status of the system component. Processes that can be monitored include a chamber cleaning process, a chamber conditioning process, a substrate etching process, and a substrate film formation process. The system component can be a consumable system part such as a process tube, a shield, a ring, a baffle, an injector, a substrate holder, a liner, a pedestal, a cap cover, an electrode, and a heater, any of which can further include a protective coating. The processing system includes the system component in a process chamber, a gas injection system for introducing the reactant gas, a chamber protection system for monitoring the status of the system component, and a controller for controlling the processing system in response to the status.

摘要翻译： 一种在过程中监视系统组件的状态的方法和系统。 该方法包括在过程期间将系统组分暴露于反应气体，其中反应气体能够蚀刻系统组分材料以形成侵蚀产物，并且在该过程期间监测侵蚀产物的释放以确定系统部件的状态 。 可以监测的方法包括室清洁过程，室调节过程，基板蚀刻工艺和基板成膜工艺。 系统组件可以是消耗系统部件，例如处理管，屏蔽件，环，挡板，注射器，衬底保持器，衬垫，基座，帽盖，电极和加热器 其可以进一步包括保护涂层。 处理系统包括处理室中的系统部件，用于引入反应气体的气体注入系统，用于监视系统部件的状态的室保护系统以及响应于状态来控制处理系统的控制器。

公开(公告)号：US07141765B2

公开(公告)日：2006-11-28

申请号：US10473248

申请日：2002-03-20

申请人： Toshiyuki Makiya ,  Takanori Saito ,  Karuki Eickmann ,  Sanjeev Kaushal ,  Anthony Dip ,  David L. O'meara

发明人： Toshiyuki Makiya ,  Takanori Saito ,  Karuki Eickmann ,  Sanjeev Kaushal ,  Anthony Dip ,  David L. O'meara

IPC分类号： H05B1/02 ,  A21B1/00

CPC分类号： G01K7/04 ,  G01K1/20

摘要： A antireflective film 50 is formed on a thermocouple 42 arranged in a processing vessel 1 of a heat treatment apparatus in order to improve the transient response characteristics of the thermocouple 42. In a typical embodiment, the thermocouple 42 is made by connecting a platinum wire 43A and a platinum-rhodium alloy wire 43B, and the antireflective film 50 is composed by stacking a silicon nitride layer 50C, silicon layer 50B and a silicon nitride layer 50A in that order.

摘要翻译： 为了改善热电偶42的瞬态响应特性，在设置在热处理装置的处理容器1中的热电偶42上形成防反射膜50。 在一个典型的实施例中，热电偶42是通过连接铂线43A和铂 - 铑合金线43B制成的，并且抗反射膜50由叠氮化硅层50C，硅层50B和硅 氮化物层50A。

公开(公告)号：US06974779B2

公开(公告)日：2005-12-13

申请号：US10662875

申请日：2003-09-16

申请人： David L O'Meara ,  Cory Wajda ,  Tsuyoshi Takahashi ,  Alessandro Callegari ,  Kristen Scheer ,  Sufi Zafar ,  Paul Jamison

发明人： David L O'Meara ,  Cory Wajda ,  Tsuyoshi Takahashi ,  Alessandro Callegari ,  Kristen Scheer ,  Sufi Zafar ,  Paul Jamison

IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L29/51 ,  H01L21/469

CPC分类号： H01L21/28185 ,  H01L21/02181 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31658 ,  H01L21/31662 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method is provided for forming a microstructure with an interfacial oxide layer by using a diffusion filter layer to control the oxidation properties of a substrate associated with formation of a high-k layer into the microstructure. The diffusion filter layer controls the oxidation of the surface. The interfacial oxide layer can be formed during an oxidation process that is carried out following deposition of a high-k layer onto the diffusion filter layer, or during deposition of a high-k layer onto the diffusion filter layer.

公开(公告)号：US06362071B1

公开(公告)日：2002-03-26

申请号：US09542706

申请日：2000-04-05

申请人： Bich-Yen Nguyen ,  William J. Taylor, Jr. ,  Philip J. Tobin ,  David L. O'Meara ,  Percy V. Gilbert ,  Yeong-Jyh T. Lii ,  Victor S. Wang

发明人： Bich-Yen Nguyen ,  William J. Taylor, Jr. ,  Philip J. Tobin ,  David L. O'Meara ,  Percy V. Gilbert ,  Yeong-Jyh T. Lii ,  Victor S. Wang

IPC分类号： H01L2176

CPC分类号： H01L21/76232 ,  H01L21/823481

摘要： In accordance with one embodiment of the present invention, a method is disclosed for forming a semiconductor device having an isolation region (601). A dielectric layer (108) is deposited and etched to form isolation regions (102, 605) having top portions that are narrower than their bottom portions, thereby a tapered isolation region is formed. Active regions (601, 603) are formed using an epitaxial process in the regions between the isolation regions. The resulting active regions (601, 603) have a greater amount of surface area near a top portion, than near a bottom portion. Transistors (721, 723) having opposite polarities are formed within the active areas.

摘要翻译： 根据本发明的一个实施例，公开了一种用于形成具有隔离区域（601）的半导体器件的方法。 沉积和蚀刻电介质层（108）以形成具有比其底部部分更窄的顶部部分的隔离区域（102,605），从而形成锥形隔离区域。 在隔离区域之间的区域中使用外延工艺形成有源区（601,603）。 所得活性区域（601,603）在顶部附近具有比在底部附近更大的表面积。 在有源区域内形成具有相反极性的晶体管（721,723）。

公开(公告)号：US06320784B1

公开(公告)日：2001-11-20

申请号：US09524916

申请日：2000-03-14

申请人： Ramachandran Muralidhar ,  Sucharita Madhukar ,  Bo Jiang ,  Bruce E. White ,  Srikanth B. Samavedam ,  David L. O'Meara ,  Michael Alan Sadd

发明人： Ramachandran Muralidhar ,  Sucharita Madhukar ,  Bo Jiang ,  Bruce E. White ,  Srikanth B. Samavedam ,  David L. O'Meara ,  Michael Alan Sadd

IPC分类号： G11C1100

CPC分类号： B82Y10/00 ,  G11C11/56 ,  G11C11/5671 ,  G11C16/0416 ,  G11C2216/08 ,  H01L29/7887 ,  H01L29/7888

摘要： A memory cell (101), its method of formation, and operation are disclosed. In accordance with one embodiment, the memory cell (101) comprises a first and second current carrying electrode (12) a control electrode (19), and doped discontinuous storage elements (17). In accordance with an alternative embodiment, memory cell programming is accomplished by removing or adding an average of approximately at least a first charge (30, 62, 64), which can be electron(s) or hole(s) from each of the doped discontinuous storage elements (17).

摘要翻译： 公开了一种存储单元（101），其形成方法和操作。 根据一个实施例，存储单元（101）包括第一和第二载流电极（12），控制电极（19）和掺杂的非连续存储元件（17）。 根据替代实施例，存储器单元编程通过去除或添加大约至少第一电荷（30,62,64）的平均值来实现，所述第一电荷可以是来自掺杂的每一个的电子或空穴 不连续存储元件（17）。

公开(公告)号：US5013690A

公开(公告)日：1991-05-07

申请号：US473546

申请日：1990-02-01

申请人： Arthur K. Hochberg ,  David L. O'Meara ,  David A. Roberts

发明人： Arthur K. Hochberg ,  David L. O'Meara ,  David A. Roberts

IPC分类号： H01L21/205 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318

CPC分类号： H01L21/3185 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3145 ,  H01L21/31612 ,  Y10S148/122 ,  Y10S438/934

摘要： A low temperature chemical vapor deposition process comprising heating in a chemical vapor depositon reactor a substrate upon which deposition is desired to a temperature of from about 550.degree. C. to about 750.degree. C. in a chemical vapor deposition reactor having a pressure of from about 0.1 torr to approximately atmospheric pressure, introducing into the reactor a silicon-containing feed and optionally an oxygen containing feed, said silicon containing feed consisting essentially of one or more compounds having the general formula ##STR1## wherein: R.sub.1, R.sub.2, R.sub.3 and R.sub.4 are hydrogen, azido or C-2 to C-6 alkyl, aryl or C-7 to C-10 aralkyl groups, at least one but not more than three of R.sub.1, R.sub.2, R.sub.3 and R.sub.4, being azido, and maintaining the temperature and pressure to cause a film of silicon nitride, silicon oxynitride or silicon dioxide to deposit is disclosed.

摘要翻译： 一种低温化学气相沉积方法，其包括在化学气相沉积反应器中加热基底，在基底上沉积希望在约550℃至约750℃的温度下在具有约 0.1托至约大气压，将含硅进料和任选的含氧进料引入反应器中，所述含硅进料基本上由一种或多种具有通式为其中的化合物组成：其中：R1，R2，R3和R4 是氢，叠氮基或C-2至C-6烷基，芳基或C-7至C-10芳烷基，R1，R2，R3和R4中至少一个但不多于三个为叠氮基，并保持温度 并且公开了使氮化硅，氮氧化硅或二氧化硅的膜沉积的压力。