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    Method and apparatus for predicting confidence and value
    21.
    发明申请
    Method and apparatus for predicting confidence and value 审中-公开
    用于预测置信度和价值的方法和装置

    公开(公告)号：US20050216714A1

    公开(公告)日：2005-09-29

    申请号：US10809957

    申请日：2004-03-25

    Applicant: Edward Grochowski

    Inventor： Edward Grochowski

    IPC: G06F9/00 ,  G06F9/38

    CPC classification number: G06F9/3863 ,  G06F9/30072 ,  G06F9/3842 ,  G06F9/3848

    Abstract: A method and apparatus for making predictions which give a predicted value and also a confidence value is presented. In one embodiment, a global confidence history is maintained. The global confidence history may be hashed with an instruction pointer to form an index into a pattern history table or tables that include local histories of confidence values and predicted values. The outputs of the pattern history tables may be used to form confidence values and predicted values.

    Abstract translation: 提出了一种提供预测值和置信度值的预测方法和装置。 在一个实施例中，保持全局置信历史。 全局置信历史可以用指令指针进行散列，以形成包含置信值和预测值的局部历史的模式历史表或表的索引。 模式历史表的输出可以用于形成置信度值和预测值。

    Circuit and method for protecting vector tags in high performance microprocessors
    22.
    发明申请
    Circuit and method for protecting vector tags in high performance microprocessors 有权
    用于保护高性能微处理器中的矢量标签的电路和方法

    公开(公告)号：US20050120184A1

    公开(公告)日：2005-06-02

    申请号：US11028293

    申请日：2005-01-04

    Applicant: Nhon Quach ,  John Crawford ,  Greg Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

    Inventor： Nhon Quach ,  John Crawford ,  Greg Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

    IPC: G06F12/08 ,  G06F12/00

    CPC classification number: G06F12/0891

    Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.

    Abstract translation: 本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。 这些保护方案保护缓存中标签阵列中使用的1-hot向量，并设计为提供硬件节省，以更高的速度运行并且易于实现。 根据本发明的一个实施例，一种标签阵列存储器，包括一个输入转换电路，用于接收1个热矢量，并将该1个热矢量转换为2个热矢量。 标签阵列存储器还包括耦合到输入转换电路的存储器阵列，存储器阵列以存储2-热矢量; 以及耦合到存储器阵列的输出转换电路，所述输出转换电路接收所述2-热矢量并将所述2-热矢量转换回所述1-热矢量。

    Method and apparatus for performing subtraction in redundant form arithmetic
    23.
    发明授权
    Method and apparatus for performing subtraction in redundant form arithmetic 有权
    用于以冗余形式算术进行减法的方法和装置

    公开(公告)号：US06754689B2

    公开(公告)日：2004-06-22

    申请号：US09745697

    申请日：2000-12-22

    Applicant: Bharat Bhushan ,  Edward Grochowski ,  John Crawford

    Inventor： Bharat Bhushan ,  Edward Grochowski ,  John Crawford

    IPC: G06F750

    CPC classification number: G06F7/50 ,  G06F7/4824

    Abstract: A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in redundant form to subtract numbers received in redundant form, including numbers received from a bypass circuit. The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing an adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit to generate a valid outcome in redundant form of a subtraction operation. A carry-save adder structure is used in one preferred embodiment of the current invention to perform a subtraction operation A−B, where B is a number represented by one of its valid carry-sum redundant representations. In order to perform the subtraction operation, each of the carry bits and each of the sum bits in a redundant representation of B are complemented and supplied to the carry-save adder. Then a result is corrected by adding an adjustment of three. This adjustment value is incorporated into the result through the carry-save adder circuit. Thus the circuit produces a valid redundant representation for the subtraction operation A−B.

    Abstract translation: 公开了一种方法和装置，其使用运算电路来添加以冗余形式表示的数字，以减去以冗余形式接收的数字，包括从旁路电路接收的数字。 该方法包括以冗余的形式生成提供给运算电路的至少一个数的补码冗余形式。 它还包括向算术电路提供调整输入以增加通过算术电路产生的结果，以产生冗余形式的减法运算来产生有效结果。在本发明的一个优选实施例中使用进位保存加法器结构 执行减法运算AB，其中B是由其有效进位和冗余表示之一表示的数。 为了执行减法运算，B的冗余表示中的每个进位位和每个和位被补码并提供给进位存储加法器。 然后通过添加三个调整来校正结果。 该调整值通过进位保存加法器电路并入结果。 因此，该电路产生用于减法运算A-B的有效冗余表示。

    Rotators in machine instruction length calculation
    24.
    发明授权
    Rotators in machine instruction length calculation 失效
    旋转器在机器指令长度计算

    公开(公告)号：US5535347A

    公开(公告)日：1996-07-09

    申请号：US335305

    申请日：1994-11-07

    Applicant: Edward Grochowski ,  Ahmad Zaidi ,  James Lan

    Inventor： Edward Grochowski ,  Ahmad Zaidi ,  James Lan

    IPC: G06F9/32 ,  G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/3822 ,  G06F9/30149 ,  G06F9/3816

    Abstract: A circuit for determining the length of an instruction including apparatus for providing a sequence of instruction bytes greater than a single instruction length, rotator apparatus for selecting a sequential number of instruction bytes for decoding commencing at a byte which begins a first instruction, control apparatus for operating the rotator, and apparatus responsive to a decoded length value derived from the first instruction for causing the control apparatus to cause the rotator to rotate to the beginning of a next instruction.

    Abstract translation: 一种用于确定包括用于提供大于单个指令长度的指令字节序列的装置的指令的电路的电路，用于选择从开始第一指令的字节开始进行解码的指令字节的顺序数目的转动装置的转动装置; 操作旋转器，以及响应于从第一指令导出的解码长度值的装置，使得控制装置使旋转体旋转到下一个指令的开始。

    Apparatus for generating computer clock pulses
    25.
    发明授权
    Apparatus for generating computer clock pulses 失效
    用于产生计算机时钟脉冲的装置

    公开(公告)号：US4985640A

    公开(公告)日：1991-01-15

    申请号：US472598

    申请日：1990-04-04

    Applicant: Edward Grochowski ,  Rajesh Gupta

    Inventor： Edward Grochowski ,  Rajesh Gupta

    IPC: H03K5/15 ,  H03K5/151

    CPC classification number: H03K5/151 ,  H03K5/15006

    Abstract: A circuit for generating a pair of clock pulses of opposite phases each having the same frequency as the frequency of an input signal generated by a crystal oscillator including apparatus for generating first and second pair of signals at half the frequency of the input signal generated by a crystal oscillator, the signals of each pair being of opposite phase to one another; apparatus for comparing a first signal of the first pair signals with the one of the signals of the second pair of signals which is normally out of phase therewith to produce an output signal only when the two signals are in phase; apparatus for comparing the second signal of the first pair of signals with the one of the signals of the second pair of signals which is normally out of phase therewith to produce an output signal only when the two signals are in phase; apparatus utilizing one of the output signals to lengthen the duty cycle of one of the first pair of signals of opposite phases and the other of the output signals to shorten the duty cycle of the other of the first pair of signals of opposite phases; apparatus for producing a pair of clock pulses of opposite phases each having the same frequency as the frequency of an input signal generated by a crystal oscillator; and apparatus responsive to the apparatus utilizing one of the output signals to lengthen the duty cycle of one of the first pair signals of opposite phases and the other of the output signals to shorten the duty cycle of the other of the first pair of signals of opposite phases for equalizing the duty cycle of the pair of closk pulses of opposite phases each having the same frequency as the frequency of an input signal generated by a crystal oscillator.

    Abstract translation: 一种用于产生相对相位的一对时钟脉冲的电路，每个时钟脉冲具有与由晶体振荡器产生的输入信号的频率相同的频率，该晶体振荡器包括用于产生第一和第二对信号的信号，所述第一和第二对信号的频率为由 晶体振荡器，每对信号彼此相反; 用于将第一对信号的第一信号与通常与其相异相的第二对信号的信号之一进行比较以仅在两个信号同相时产生输出信号的装置; 用于将第一对信号的第二信号与通常与其相异相的第二对信号的信号之一进行比较以仅在两个信号同相时产生输出信号的装置; 利用所述输出信号之一来延长所述第一对相对相位信号中的一个的占空比以及所述输出信号中的另一个的占空比，以缩短所述第一对相对相位信号中另一个的占空比; 用于产生具有与由晶体振荡器产生的输入信号的频率相同频率的相反相位的一对时钟脉冲的装置; 以及响应于所述装置的设备，利用所述输出信号之一来延长所述第一对相对相位信号之一的占空比，并且输出信号中的另一个信号的占空比，以缩短所述第一对信号中另一个的相反的占空比 用于均衡相位相对的一对闭合脉冲的占空比的相位，每个相位相位的频率与由晶体振荡器产生的输入信号的频率相同。

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