Abstract:
A drive control circuit generates switching drive signals for a single phase of a multiphase voltage regulator. A driver circuitry generates the switching drive signals for the voltage regulator responsive to a clock signal. A clock circuitry generates the clock signal responsive to a monitored external clock signal. A phase number detector determines a number of active phases in the multiphase voltage regulator in real time responsive to an indicator on a phase number input monitored by the phase detector.
Abstract:
A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.
Abstract:
A sigma-delta converter may include a filter coupled to a first summation circuit and a second summation circuit. A multi bit quantizer may be coupled to the second summation circuit. A single bit digital-to-analog converter (DAC) may be included that defines a feedback path between the multi-bit quantizer and the first summation circuit. A feed-forward coefficient circuit defining a feed forward path between the first summation circuit and the second summation circuit may be included.
Abstract:
A configurable photo detector circuit comprises a photo detector array including a plurality of photo detectors coupled to a plurality of amplifiers. A method for programming a detection pattern of the configurable photo detector circuit comprises selecting a first detection pattern for the photo detector array, generating first signals to create the first selected detection pattern, and applying the first generated signals to the photo detector circuit to implement the first selected detection pattern.
Abstract:
An isolated epitaxial modulation device comprises a substrate; a barrier structure formed on the substrate; an isolated epitaxial region formed above the substrate and electrically isolated from the substrate by the barrier structure; a semiconductor device, the semiconductor device located in the isolated epitaxial region; and a modulation network formed on the substrate and electrically coupled to the semiconductor device. The device also comprises a bond pad and a ground pad. The isolated epitaxial region is electrically coupled to at least one of the bond pad and the ground pad. The semiconductor device and the epitaxial modulation network are configured to modulate an input voltage.
Abstract:
Provided herein are methods and systems that provide automatic compensation for frequency attenuation of a video signal transmitted over a cable. In accordance with an embodiment, a system includes an equalizer and a compensation controller. The equalizer receives a video signal that was transmitted over a cable, provides compensation for frequency attenuation that occurred during the transmission over the cable, and outputs a compensated video signal. The compensation controller automatically adjusts the compensation provided by the equalizer based on comparisons of one or more portions of the compensated video signal to one or more reference voltage levels.
Abstract:
Systems and methods for determining an unknown QPSK or QAM constellation from a set of possible received constellations are described. One method utilizes a histogram of the power of the signal after inter-symbol-interference has been minimized with a modified constant modulus algorithm equalizer. The constellation may be determined before carrier frequency and phase has been fully recovered. An unknown QPSK or QAM constellation may be identified before or after equalization using disclosed methods for analyzing an output power histogram.
Abstract:
A high bandwidth, feed-forward oscillator generates a ramp or sawtooth voltage for controlling the operation of a pulse width modulator-based, switched DC power supply circuit. The oscillator is operative to effectively immediately adjust the slope of each rising and falling portion of the ramp/sawtooth signal, as necessary, in proportion to the magnitude of the input voltage, while maintaining the frequency of the ramp waveform effectively constant. A comparator network establishes a difference between peak and valley portions of the sawtooth in accordance with input voltage. In response to a change in input voltage a control circuit modifies the value of the difference between the peak and valley portions to define a new set of respective peak and valley portions VpeakNEW and VvalleyNEW, and immediately causes the sawtooth waveform to transition to the new set of respective peak and valley portions VpeakNEW and VvalleyNEW at said prescribed frequency.
Abstract:
An arrangement for measuring current through a phase section of a buck mode DC-DC converter includes an auxiliary integrated circuit containing an auxiliary power MOSFET and a pilot MOSFET coupled in parallel with a current path through a high side MOSFET of a half-bridge of the converter. The pilot MOSFET has a current path coupled to a current measurement terminal. The MOSFETs of the auxiliary circuit are time division multiplexed with the high side MOSFET, whereby a determination of current through the auxiliary high side MOSFET is based upon current through the pilot device and the geometric ratio of the size of the pilot device to that of the high side auxiliary MOSFET. The high side MOSFET is activated for a large number of switching cycles relative to the pilot circuitry, but the pilot circuitry is activated sufficiently often to derive a relatively accurate measure of current flow.
Abstract:
A regulator supplies a regulated voltage to an electronic component with a plurality of phases with varying response rates. The regulator includes an output node that provides a regulated supply voltage, a first main-phase drive circuit that provides a first main load current to the output node and that has an on time and an off time, and a first transient-phase drive circuit that has a first transient load current to the output node that has an on time and an off time that are respectively less than the on and off times of the first main-phase drive circuit.