公开(公告)号：US07615441B2

公开(公告)日：2009-11-10

申请号：US11998236

申请日：2007-11-29

Applicant: Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Uday Shah ,  Gilbert Dewey ,  Robert S. Chau

Inventor： Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Uday Shah ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L21/8242

CPC classification number: H01L21/0228 ,  H01L21/02052 ,  H01L21/02175 ,  H01L21/28167 ,  H01L21/3141 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.

Abstract translation: 可以在平滑的硅衬底上形成缓冲层和高k金属氧化物电介质。 衬底平滑度可能降低高k金属氧化物栅极电介质的柱生长。 在沉积之前，衬底的表面可能被羟基终止物饱和。

公开(公告)号：US07595248B2

公开(公告)日：2009-09-29

申请号：US11293753

申请日：2005-12-01

Applicant: Michael L. Hattendorf ,  Justin K. Brask ,  Justin S. Sandford ,  Jack Kavalieros ,  Matthew V. Metz

Inventor： Michael L. Hattendorf ,  Justin K. Brask ,  Justin S. Sandford ,  Jack Kavalieros ,  Matthew V. Metz

IPC: H01L21/265

CPC classification number: H01L21/28114 ,  H01L21/26586 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32136 ,  H01L21/32137 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more angled ion implants, then removing the altered portions of the blanket dielectric layer.

Abstract translation: 本发明的实施例提供一种具有反向锥形栅极电极和栅极电介质层的器件，其长度接近栅极长度。 在一个实施例中，这可以通过用一个或多个成角度的离子注入来改变覆盖介电层的部分，然后去除覆盖介电层的改变的部分来完成。

公开(公告)号：US20090075445A1

公开(公告)日：2009-03-19

申请号：US12313368

申请日：2008-11-19

Applicant: Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Brian S. Doyle ,  Robert S. Chau ,  Everett X. Wang ,  Philippe Matagne ,  Lucian Shifren ,  Been Y. Jin ,  Mark Stettler ,  Martin D. Giles

Inventor： Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Brian S. Doyle ,  Robert S. Chau ,  Everett X. Wang ,  Philippe Matagne ,  Lucian Shifren ,  Been Y. Jin ,  Mark Stettler ,  Martin D. Giles

IPC: H01L21/336

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  Y10S438/933

Abstract: A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

Abstract translation: 晶体管可以由不同的硅锗层形成，具有梯度锗浓度的最低层和具有恒定锗浓度的上层，使得最底层具有Si1-xGex形式。 最高层可以是PMOS侧的Si1-yGey形式。 源极和漏极可以由PMOS侧的Si1-zGez形式的外延硅锗形成。 在一些实施例中，在PMOS器件中，x大于y且z大于x。 因此，PMOS器件可以在沟道方向上具有单轴压应力和面内双轴压应力。 在某些情况下，这种压力的组合可能导致更高的移动性和增加的设备性能。

公开(公告)号：US20090042405A1

公开(公告)日：2009-02-12

申请号：US12157796

申请日：2008-06-12

Applicant: Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros ,  Uday Shah ,  Matthew V. Metz ,  Suman Datta ,  Ramune Nagisetty ,  Robert S. Chau

Inventor： Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros ,  Uday Shah ,  Matthew V. Metz ,  Suman Datta ,  Ramune Nagisetty ,  Robert S. Chau

IPC: H01L21/469

CPC classification number: H01L21/823842

Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成第一电介质层，在第一介电层内形成沟槽，在衬底上形成第二电介质层。 第二电介质层具有形成在沟槽中的第一部分和第二部分。 在第二电介质层的第一和第二部分上形成具有第一功函数的第一金属层之后，第一金属层的一部分被转换成具有第二功函数的第二金属层。

公开(公告)号：US07442983B2

公开(公告)日：2008-10-28

申请号：US11390892

申请日：2006-03-27

Applicant: Mark L. Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew V. Metz ,  Adrian B. Sherrill ,  Markus Kuhn ,  Robert S. Chau

Inventor： Mark L. Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew V. Metz ,  Adrian B. Sherrill ,  Markus Kuhn ,  Robert S. Chau

IPC: H01L27/108

CPC classification number: H01L21/0214 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3144 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517 ,  H01L29/518

Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成氧化物层，并在氧化物层上形成高k电介质层。 然后将氧化物层和高k电介质层在足够的温度下退火足够的时间以产生具有渐变介电常数的栅极电介质。

公开(公告)号：US07427794B2

公开(公告)日：2008-09-23

申请号：US11123565

申请日：2005-05-06

Applicant: Robert S. Chau ,  Brian S. Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott A. Hareland

Inventor： Robert S. Chau ,  Brian S. Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott A. Hareland

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/7854 ,  H01L29/78645 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0554 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

Abstract: The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

Abstract translation: 本发明是一种半导体器件，其包括半导体本体，其具有形成在衬底上的顶表面和横向相对的侧壁。 栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。 栅极电极形成在半导体本体的顶表面上的栅电介质上并与半导体本体的横向相对的侧壁上的栅电介质相邻。

公开(公告)号：US07422936B2

公开(公告)日：2008-09-09

申请号：US10925517

申请日：2004-08-25

Applicant: Chris E. Barns ,  Matt Prince ,  Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros

Inventor： Chris E. Barns ,  Matt Prince ,  Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros

IPC: H01L21/338

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/517 ,  H01L29/78

Abstract: Replacement metal gates may be formed by removing a polysilicon layer from a gate structure. The gate structure may be formed by patterning the polysilicon layer and depositing a spacer layer over the gate structure such that the spacer layer has a first polish rate. The spacer layer is then etched to form a sidewall spacer. An interlayer dielectric is applied over the gate structure with the sidewall spacer. The interlayer dielectric has a second polish rate higher than the first polish rate. A hard mask may also be applied over the gate structure and implanted so that the hard mask may be more readily removed.

Abstract translation: 可以通过从栅极结构去除多晶硅层来形成替代金属栅极。 栅极结构可以通过图案化多晶硅层并在栅极结构上沉积间隔层形成，使得间隔层具有第一抛光速率。 然后对间隔层进行蚀刻以形成侧壁间隔物。 在栅极结构上用侧壁间隔物施加层间电介质。 层间电介质具有比第一抛光速率高的第二抛光速率。 硬掩模也可以施加在栅极结构上并被植入，使得硬掩模可以更容易地去除。

公开(公告)号：US20080211033A1

公开(公告)日：2008-09-04

申请号：US12151483

申请日：2008-05-07

Applicant: Robert B. Turkot ,  Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Uday Shah ,  Suman Datta ,  Robert S. Chau

Inventor： Robert B. Turkot ,  Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Uday Shah ,  Suman Datta ,  Robert S. Chau

IPC: H01L27/092

CPC classification number: H01L21/28079 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517

Abstract: A metal layer is formed on a dielectric layer, which is formed on a substrate. After forming a masking layer on the metal layer, the exposed sides of the dielectric layer are covered with a polymer diffusion barrier.

Abstract translation: 在形成在基板上的电介质层上形成金属层。 在金属层上形成掩模层之后，介电层的暴露侧面被聚合物扩散阻挡层覆盖。

公开(公告)号：US20080124857A1

公开(公告)日：2008-05-29

申请号：US11556025

申请日：2006-11-02

Applicant: Justin K. Brask ,  Mark L. Doczy ,  Jack Kavalieros ,  Matthew V. Metz ,  Chris E. Barns ,  Uday Shah ,  Suman Datta ,  Christopher D. Thomas ,  Robert S. Chau

Inventor： Justin K. Brask ,  Mark L. Doczy ,  Jack Kavalieros ,  Matthew V. Metz ,  Chris E. Barns ,  Uday Shah ,  Suman Datta ,  Christopher D. Thomas ,  Robert S. Chau

IPC: H01L21/77 ,  H01L21/762 ,  H01L21/04

CPC classification number: H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/1203 ,  H01L29/4975 ,  H01L29/66545 ,  Y10S438/926

Abstract: A semiconductor device and a method for forming it are described. The semoiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.

Abstract translation: 对半导体装置及其形成方法进行说明。 半导体器件包括形成在衬底的第一部分上的金属NMOS栅极电极和形成在衬底的第二部分上的硅化物PMOS栅极电极。

公开(公告)号：US20080085580A1

公开(公告)日：2008-04-10

申请号：US11529963

申请日：2006-09-29

Applicant: Brian Doyle ,  Robert Chau ,  Suman Datta ,  Jack Kavalieros

Inventor： Brian Doyle ,  Robert Chau ,  Suman Datta ,  Jack Kavalieros

IPC: H01L21/8238 ,  H01L29/94

CPC classification number: H01L21/823437 ,  H01L21/2236 ,  H01L21/26586 ,  H01L29/66803 ,  H01L29/7851

Abstract: Methods for uniformly tip doping a silicon body of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include vertical tip ion implantation of a silicon body with at least three surfaces on a substrate followed by conformal deposition of a dielectric material. The dielectric material can be selectively etched to expose a top surface of the silicon body followed by selective re-oxidation of the top surface for form a mask. The remaining dielectric material can be removed followed by angled ion implantation of at least two sidewalls of the silicon body. The mask can be removed resulting in a silicon body with uniform doping.

Abstract translation: 用于均匀尖端掺杂非平面晶体管的硅体的方法以及通过这种方法形成的器件和系统。 在一个实施例中，一种方法可以包括在衬底上具有至少三个表面的硅体的垂直尖端离子注入，随后是电介质材料的共形沉积。 可以选择性地蚀刻介电材料以暴露硅体的顶表面，随后选择性地再次氧化顶表面以形成掩模。 可以除去剩余的电介质材料，然后对硅体的至少两个侧壁进行成角度的离子注入。 可以去除掩模，从而产生均匀掺杂的硅体。