公开(公告)号：US20050285181A1

公开(公告)日：2005-12-29

申请号：US11147243

申请日：2005-06-08

Applicant: Kan Yasui ,  Digh Hisamoto ,  Toshihiro Tanaka ,  Takashi Yamaki

Inventor： Kan Yasui ,  Digh Hisamoto ,  Toshihiro Tanaka ,  Takashi Yamaki

IPC: G11C16/02 ,  G11C16/04 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C16/3418 ,  G11C16/0466 ,  G11C16/3427 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/792

Abstract: In a non-volatile semiconductor memory device using a charge storage film, it is intended to prevent a sequence disturb such as an erroneous write or erase of another memory cell on one and same word line which occurs depending on a bias transition path in stand-by state and write state. In connection with rise and fall of a word line bias, the present invention adopts a procedure such that a diffusion region voltage Vs on a memory transistor side is changed, and after the voltage Vs passes a certain intermediate value Vsx, a gate voltage Vmg of the memory transistor is changed. Alternatively, there is adopted a procedure such that the gate voltage Vmg of the memory transistor is changed, and after the voltage Vmg passes a certain intermediate value Vmgx, the diffusion layer voltage Vs on the memory transistor side is changed. The values of Vsx and Vmgx are determined from the magnitude of the electric field in a gate insulating film not causing FN tunneling electron injection that causes a change in threshold voltage and the magnitude of a potential barrier against holes not causing BTBT hot hole injection.

Abstract translation: 在使用电荷存储膜的非易失性半导体存储器件中，旨在防止在根据独立的偏置过渡路径发生的同一字线上的另一个存储单元的错误写入或擦除的序列干扰， 按状态和写状态。 关于字线偏差的上升和下降，本发明采用使存储晶体管侧的扩散区电压Vs变化的过程，在电压Vs经过一定的中间值Vsx之后，栅极电压Vmg为 存储晶体管被改变。 或者，采用使存储晶体管的栅极电压Vmg改变的过程，并且在电压Vmg经过一定的中间值Vmgx之后，存储晶体管侧的扩散层电压Vs被改变。 Vsx和Vmgx的值由栅极绝缘膜中不引起FN隧穿电子注入的电场的大小确定，导致阈值电压的变化以及针对未引起BTBT热空穴注入的孔的势垒的大小。

公开(公告)号：US06723144B2

公开(公告)日：2004-04-20

申请号：US10308088

申请日：2002-12-03

Applicant: Souichi Katagiri ,  Kan Yasui ,  Ryousei Kawai ,  Sadayuki Nishimura ,  Masahiko Sato ,  Yoshio Kawamura ,  Shigeo Moriyama

Inventor： Souichi Katagiri ,  Kan Yasui ,  Ryousei Kawai ,  Sadayuki Nishimura ,  Masahiko Sato ,  Yoshio Kawamura ,  Shigeo Moriyama

IPC: B24D302

CPC classification number: B24B37/245 ,  B24D3/32 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76819 ,  H01L21/7684

Abstract: A film formed on a surface of a wafer on which an integrated circuit is to be constructed can be planarized by using a fixed abrasive tool regardless of the width of elements of a pattern underlying the film. The fixed abrasive tool is liable to form scratches in the surface of the film. A planarizing process of the present invention employs a fixed abrasive tool containing substances harder than the film to be planarized in a content of 10 ppm or below and having a mean pore diameter of 0.2 &mgr;m or below.

Abstract translation: 形成在其上将要构造集成电路的晶片的表面上的膜可以通过使用固定的研磨工具进行平面化，而与薄膜下面的图案的元件的宽度无关。 固定的研磨工具易于在膜表面形成划痕。 本发明的平面化方法使用含有比待平坦化的膜更硬的物质的固定研磨工具，其含量为10ppm以下，平均孔径为0.2μm以下。

公开(公告)号：US6099393A

公开(公告)日：2000-08-08

申请号：US80728

申请日：1998-05-21

Applicant: Soichi Katagiri ,  Shigeo Moriyama ,  Kan Yasui ,  Katsuhiko Yamaguchi

Inventor： Soichi Katagiri ,  Shigeo Moriyama ,  Kan Yasui ,  Katsuhiko Yamaguchi

IPC: B24B37/00 ,  B24B53/007 ,  B24B53/013 ,  H01L21/304 ,  B24B1/00

CPC classification number: B24B53/017 ,  B24B53/013

Abstract: In the polishing machine 10 for pressing the polished surface 7 of the workpiece 1 against the face where there are abrasives 15 of the rotating polishing tool 11 and executing chemical mechanical polishing, the brushing device 30, the cleaner 40, the abrasive supplier 52, and the pure water supplier 60 are sequentially arranged behind the location of the head 20 for pressing the workpiece 1 against the polishing tool 11 in the rotational direction. The cleaner 40 sprays the cleaning water 47 to the face where there are abrasives 15 of the rotating polishing tool 11 and sucks and collects it by the vacuum hole 45. Fresh slurry 62 is always supplied by the slurry supplier 63 comprising the abrasive supplier 52 and the pure water supplier 60.

Abstract translation: 在用于将工件1的抛光表面7压靠在旋转抛光工具11的磨料15的表面上并执行化学机械抛光的抛光机10中，刷洗装置30，清洁器40，磨料供应器52和 纯水供应器60顺序地布置在头部20的位置之后，用于将工件1沿着旋转方向压靠在抛光工具11上。 清洁器40将清洗水47喷射到旋转研磨工具11的磨料15的表面，并通过真空孔45吸收并收集。新鲜浆料62总是由包含磨料供应器52的浆料供给器63供应， 纯水供应商60。

公开(公告)号：US08796756B2

公开(公告)日：2014-08-05

申请号：US13755348

申请日：2013-01-31

Applicant: Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasafumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

Inventor： Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasafumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

IPC: H01L29/792

CPC classification number: H01L29/66833 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/792

Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

Abstract translation: 插入在存储栅电极和半导体衬底之间的电荷存储层形成为比存储栅电极的栅极长度或绝缘膜的长度短，以使电荷存储层和源极区域的重叠量成为 小于40nm。 因此，在写入状态下，由于在电荷存储层中局部存在的电子和空穴的横向的移动减少，因此可以降低保持高温时的阈值电压的变化。 此外，有效沟道长度为30nm以下，以减少空穴的表观量，使得电子与电荷存储层中的空穴的耦合减小; 因此，可以降低在室温下保持时的阈值电压的变化。

公开(公告)号：US08472258B2

公开(公告)日：2013-06-25

申请号：US13269425

申请日：2011-10-07

Applicant: Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

Inventor： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

Abstract translation: 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US08324092B2

公开(公告)日：2012-12-04

申请号：US12652517

申请日：2010-01-05

Applicant: Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-Ichiro Kimura

Inventor： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-Ichiro Kimura

IPC: H01L21/00

CPC classification number: H01L27/115 ,  G11C16/0425 ,  H01L27/11568 ,  H01L29/42344

Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

Abstract translation: 提供一种制造非挥发性半导体存储器件的方法，其克服了由于最佳栅极高度的差异而引入的离子的渗透问题，同时形成利用侧壁结构的自对准分裂栅型存储单元和 缩放MOS晶体管。 形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于 在逻辑区域的栅电极。 栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。

公开(公告)号：US08284527B2

公开(公告)日：2012-10-09

申请号：US12957229

申请日：2010-11-30

Applicant: Nobuo Yoshida ,  Masato Shiimoto ,  Kenichi Akita ,  Kan Yasui

Inventor： Nobuo Yoshida ,  Masato Shiimoto ,  Kenichi Akita ,  Kan Yasui

IPC: G11B5/39

CPC classification number: H01L43/08 ,  B82Y25/00 ,  G01R33/093 ,  G01R33/098 ,  G11B5/3912 ,  G11B5/398

Abstract: A magnetic head, according to one embodiment, includes a sensor film, a sensor cap film provided above the sensor film, a pair of shields including an upper magnetic shield and a lower magnetic shield which serve as electrodes that pass current in a film thickness direction of the sensor film, a track insulating film contacting both sides of the sensor film in the track width direction, a graded domain control film arranged on both sides in the track width direction of the sensor film adjacent the track insulating film, and an element height direction insulating film positioned on an opposite side of the sensor film relative to an air-bearing surface, wherein an edge position of the element height direction insulating film adjacent the sensor film on the air-bearing surface side is substantially the same as an edge position of the sensor cap film in the element height direction.

Abstract translation: 根据一个实施例的磁头包括传感器膜，设置在传感器膜上方的传感器盖膜，包括上磁屏蔽和下磁屏蔽的一对屏蔽件，其用作使电流在膜厚度方向上通过的电极 传感器膜的传感器膜的两侧接触的轨道绝缘膜，布置在邻近轨道绝缘膜的传感器膜的轨道宽度方向两侧的梯度控制膜和元件高度 相对于空气轴承表面定位在传感器膜的相对侧上的方向绝缘膜，其中与空气轴承表面侧相邻的传感器膜的元件高度方向绝缘膜的边缘位置与边缘位置基本相同 传感器盖膜在元件高度方向上。

公开(公告)号：US20120086070A1

公开(公告)日：2012-04-12

申请号：US13328104

申请日：2011-12-16

Applicant: Digh HISAMOTO ,  Shinichiro KIMURA ,  Kan YASUI ,  Nozomu MATSUZAKI

Inventor： Digh HISAMOTO ,  Shinichiro KIMURA ,  Kan YASUI ,  Nozomu MATSUZAKI

IPC: H01L29/792

CPC classification number: H01L27/11531 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/792

Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

Abstract translation: 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

公开(公告)号：US08125012B2

公开(公告)日：2012-02-28

申请号：US11639134

申请日：2006-12-15

Applicant: Toshiyuki Mine ,  Kan Yasui ,  Tetsuya Ishimaru ,  Yasuhiro Shimamoto

Inventor： Toshiyuki Mine ,  Kan Yasui ,  Tetsuya Ishimaru ,  Yasuhiro Shimamoto

IPC: H01L21/336 ,  H01L21/31

CPC classification number: H01L29/42344 ,  H01L29/512 ,  H01L29/513 ,  H01L29/792 ,  Y10S438/954

Abstract: Performance of a non-volatile semiconductor storage device which performs electron writing by hot electrons and hole erasure by hot holes is improved. A non-volatile memory cell which performs a writing operation by electrons and an erasure operation by holes has a p-type well region, isolation regions, a source region, and a drain region provided on an Si substrate. A control gate electrode is formed via a gate insulating film between the source region and the drain region. In a left-side side wall of the control gate electrode, a bottom Si oxide film, an electric charge holding film, a top Si oxide film, and a memory gate electrode are formed. The electric charge holding film is formed from an Si nitride film stoichiometrically excessively containing silicon.

Abstract translation: 通过热电子进行电子写入和通过热孔进行空穴擦除的非易失性半导体存储装置的性能得到改善。 通过电子执行写入操作和通过空穴的擦除操作的非易失性存储单元具有设置在Si衬底上的p型阱区域，隔离区域，源极区域和漏极区域。 通过栅极绝缘膜在源极区域和漏极区域之间形成控制栅电极。 在控制栅电极的左侧壁形成有底部的氧化硅膜，电荷保持膜，顶部氧化物膜和存储栅电极。 电荷保持膜由化学计量过度地含有硅的氮化硅膜形成。

公开(公告)号：US20120026798A1

公开(公告)日：2012-02-02

申请号：US13269425

申请日：2011-10-07

Applicant: Digh HISAMOTO ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

Inventor： Digh HISAMOTO ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC: G11C16/10

CPC classification number: G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

Abstract translation: 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。