公开(公告)号：US06225204B1

公开(公告)日：2001-05-01

申请号：US09168226

申请日：1998-10-07

Applicant: Kun-Lin Wu ,  Horng-Bor Lu

Inventor： Kun-Lin Wu ,  Horng-Bor Lu

IPC: H01L2144

CPC classification number: H01L21/76825 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76831

Abstract: A method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as an implantation process, on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densified surface of the dielectric layer is able to efficiently prevent the occurrence of poisoned trenches and vias caused by the outgassing phenomena.

Abstract translation: 一种用于防止在双镶嵌工艺中发生中毒的沟槽和通孔的方法，该方法包括在开口充满导电材料之前在开口周围的暴露介电层的表面上执行诸如注入工艺的致密化过程。 电介质层的致密表面能够有效地防止由脱气现象引起的中毒的沟槽和通孔的发生。

公开(公告)号：US06180467B2

公开(公告)日：2001-01-30

申请号：US09211641

申请日：1998-12-15

Applicant: Kun-Lin Wu ,  Horng-Bor Lu

Inventor： Kun-Lin Wu ,  Horng-Bor Lu

IPC: H01L21336

CPC classification number: H01L21/76224

Abstract: A method for fabricating a shallow trench isolation in a semiconductor substrate. A mask layer is formed on the substrate. The mask layer is patterned and used as a mask in order to form a trench in the substrate. A portion of the substrate is removed to form the trench in the substrate. A liner layer is formed on the substrate exposed by the trench and optionally, an additonal liner layer is formed on the liner layer. A doped isolation layer is formed to fill the trench. A densification step is performed. The mask layer is removed. The doped isolation layer has a lower glass transition temperature so that the temperature of the densification step is reduced to about 700° C. to 1000° C.

Abstract translation: 一种用于在半导体衬底中制造浅沟槽隔离的方法。 在基板上形成掩模层。 将掩模层图案化并用作掩模，以便在衬底中形成沟槽。 去除衬底的一部分以在衬底中形成沟槽。 在由沟槽暴露的衬底上形成衬里层，并且任选地，在衬垫层上形成附加衬里层。 形成掺杂隔离层以填充沟槽。 进行致密化步骤。 去除掩模层。 掺杂隔离层具有较低的玻璃化转变温度，使得致密化步骤的温度降低至约700℃至1000℃。

公开(公告)号：US6150259A

公开(公告)日：2000-11-21

申请号：US191162

申请日：1998-11-13

Applicant: Kun-Lin Wu ,  Horng-Bor Lu

Inventor： Kun-Lin Wu ,  Horng-Bor Lu

IPC: H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76862 ,  H01L21/76843 ,  H01L21/76856

Abstract: A method for forming a metal plug is provided. The method is used to form a metal plug without a hole on a glue/barrier layer within a trench when the glue/barrier layer has been formed for a while. A substrate with a trench therein and a glue/barrier layer formed conformal to the profile of the substrate is provided. A post-treatment is performed on the glue/barrier layer to prevent moisture absorption and to make the glue/barrier become dense. The post-treatment comprises a plasma treatment or a deep UV plus laser treatment. After performing the post-treatment step, a metal layer is formed on the glue/barrier layer at least to fill in the trench. The metal layer other than that filling the trench is removed to form a metal plug.

Abstract translation: 提供一种用于形成金属插头的方法。 该方法用于当胶/阻隔层已经形成一段时间时，在沟槽内的胶/阻挡层上形成没有孔的金属塞。 提供其中具有沟槽的衬底和与衬底的轮廓保形的形成的胶/阻挡层。 在胶/阻隔层上进行后处理以防止吸湿并使胶/屏障变得致密。 后处理包括等离子体处理或深UV加激光处理。 在执行后处理步骤之后，至少在胶/阻挡层上形成金属层以填充沟槽。 去除填充沟槽以外的金属层以形成金属塞。

公开(公告)号：US6013581A

公开(公告)日：2000-01-11

申请号：US166821

申请日：1998-10-05

Applicant: Kun-Lin Wu ,  Horng-Bor Lu

Inventor： Kun-Lin Wu ,  Horng-Bor Lu

IPC: H01L21/768 ,  H05K3/00 ,  H05K3/38 ,  H05K3/46 ,  H01B13/00

CPC classification number: H01L21/76826 ,  H01L21/76813 ,  H01L21/76831 ,  H05K3/465 ,  H05K2203/0384 ,  H05K2203/095 ,  H05K3/002 ,  H05K3/388

Abstract: A method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as an plasma treatment, on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densified surface of the dielectric layer is able to efficiently prevent the occurrence of poisoned trenches and vias caused by the outgassing phenomena.

Abstract translation: 一种用于防止在双镶嵌工艺中发生中毒的沟槽和通孔的方法，该方法包括在开口充满导电材料之前，在开口周围的暴露介电层的表面上进行致密化处理，例如等离子体处理。 电介质层的致密表面能够有效地防止由脱气现象引起的中毒的沟槽和通孔的发生。

公开(公告)号：US5883004A

公开(公告)日：1999-03-16

申请号：US920172

申请日：1997-08-25

Applicant: Hao-Kuang Shiu ,  Kun-Lin Wu ,  Horng-Bor Lu ,  Jenn-Tarng Lin

Inventor： Hao-Kuang Shiu ,  Kun-Lin Wu ,  Horng-Bor Lu ,  Jenn-Tarng Lin

IPC: H01L21/3105 ,  H01L21/768 ,  H01L21/00

CPC classification number: H01L21/31053 ,  H01L21/76819

Abstract: A method for planarizing interlayer dielectric is disclosed. The present invention includes firstly forming a barrier layer over a semiconductor substrate. Next, a buffer layer is formed on the barrier layer by a spin-on-glass technique. A dielectric layer is formed on the buffer layer, wherein etch rate of the dielectric layer is larger than etch rate of the buffer layer, and the barrier layer serves as a block of autodoping coming from the dielectric layer. Finally, the dielectric layer is etched back using the buffer layer as buffer, thereby planarizing the dielectric layer.

Abstract translation: 公开了一种平面化层间电介质的方法。 本发明包括首先在半导体衬底上形成阻挡层。 接下来，通过旋涂玻璃技术在阻挡层上形成缓冲层。 在缓冲层上形成电介质层，其中介电层的蚀刻速率大于缓冲层的蚀刻速率，势垒层用作来自电介质层的自掺杂块。 最后，使用缓冲层作为缓冲层来回蚀介电层，从而平坦化介电层。

公开(公告)号：US20110291942A1

公开(公告)日：2011-12-01

申请号：US12839886

申请日：2010-07-20

Applicant: Yu CHEN ,  Kun-Lin Wu

Inventor： Yu CHEN ,  Kun-Lin Wu

IPC: G06F3/02

CPC classification number: G06F3/0489

Abstract: A display method, an application program and a computer readable medium for displaying key function are disclosed. The display method for computer key function includes steps user pressing a special keys on the keyboard, triggering an internal embedded controller in the computer and further detecting hardware function set up in the computer via a basic input output system. Thus, function descriptions are displayed on a screen according to hardware function set up in the computer, wherein the hardware function and function descriptions correspond to each function key on the keyboard. Accordingly, it is not required to replace keyboard with different printed function reminding pattern when hardware functions of the computer is changed.

Abstract translation: 公开了一种用于显示键功能的显示方法，应用程序和计算机可读介质。 用于计算机键功能的显示方法包括用户按压键盘上的特殊键的步骤，触发计算机内部嵌入式控制器，并通过基本输入输出系统进一步检测计算机中设置的硬件功能。 因此，功能描述根据计算机中设置的硬件功能在屏幕上显示，其中硬件功能和功能描述对应于键盘上的每个功能键。 因此，当计算机的硬件功能改变时，不需要用不同的打印功能提醒模式替换键盘。

公开(公告)号：US20110189854A1

公开(公告)日：2011-08-04

申请号：US13087356

申请日：2011-04-14

Applicant: Kun-Lin Wu ,  Meng-Jin Tsai

Inventor： Kun-Lin Wu ,  Meng-Jin Tsai

IPC: H01L21/768

CPC classification number: H01L21/76829 ,  H01L21/31053 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/3185 ,  H01L21/76819 ,  H01L21/7684

Abstract: A chemical-mechanical polishing process includes the steps of providing a semiconductor substrate having a first conductive line thereon, and then forming at least one dielectric layer over the substrate and the first conductive line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a cap layer is formed over the polished dielectric layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second conductive line that couples electrically with the first conductive line through the via opening.

Abstract translation: 化学机械抛光工艺包括以下步骤：提供其上具有第一导电线的半导体衬底，然后在衬底和第一导电线上形成至少一个电介质层。 接下来，使用化学 - 机械抛光方法来抛光电介质层的表面。 此后，在抛光的介电层上形成覆盖层。 形成盖层的方法包括使用硅烷（SiH4）或四乙基原硅酸盐（TEOS）作为主要反应剂的化学气相沉积法沉积氧化硅。 或者，可以通过使用化学气相沉积法以硅烷或二氯硅酸氢钠（SiH 2 Cl 2）作为主要反应剂沉积氮化硅来形成覆盖层。 最后，通过介电层和盖层形成通孔，以及通过通路孔与第一导电线电连接的第二导线。

公开(公告)号：US06241582B1

公开(公告)日：2001-06-05

申请号：US09157041

申请日：1998-09-18

Applicant: Juen-Kuen Lin ,  Chien-Hsin Lai ,  Peng-Yih Peng ,  Kun-Lin Wu ,  Daniel Chiu ,  Chih-Chiang Yang ,  Juan-Yuan Wu ,  Hao-Kuang Chiu

Inventor： Juen-Kuen Lin ,  Chien-Hsin Lai ,  Peng-Yih Peng ,  Kun-Lin Wu ,  Daniel Chiu ,  Chih-Chiang Yang ,  Juan-Yuan Wu ,  Hao-Kuang Chiu

IPC: B24B100

CPC classification number: B24B37/32 ,  B24B37/042 ,  B24B57/02

Abstract: A chemical mechanical polishing machine and a fabrication process using the same. The chemical mechanical polishing machine comprises a retainer ring having a plurality of slurry passages at the bottom of the retainer ring. The retainer ring further comprises a circular path. By conducting the slurry through the slurry passages and the circular, a wafer is planarized within the chemical mechanical polishing machine.

Abstract translation: 化学机械抛光机及其制造方法。 化学机械抛光机包括在保持环的底部具有多个浆料通道的保持环。 保持环还包括圆形路径。 通过将浆料通过浆料通道和圆形管，在化学机械抛光机内将晶片平坦化。

公开(公告)号：US06140232A

公开(公告)日：2000-10-31

申请号：US386673

申请日：1999-08-31

Applicant: Yu-Tsai Lin ,  Kun-Lin Wu

Inventor： Yu-Tsai Lin ,  Kun-Lin Wu

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/283

CPC classification number: H01L29/66515 ,  H01L21/28052 ,  H01L21/28518

Abstract: A method for forming narrow line width silicide having reduced sheet resistance is disclosed by the present invention. The method includes: firstly, providing a semiconductor substrate, whereon there formed at least a source/drain region and a gate region, as well as a spacer formed on a sidewall of the gate region; then, depositing a titanium metal layer overlying the semiconductor substrate and the resulting structure; next, carrying out rapid thermal processing and RCA cleaning to form a first titanium silicide layer; consequentially, forming a selective polysilicon layer over the first titanium silicide layer; and, depositing a second titanium metal layer over the selective polysilicon layer and overlying the exposed surface of spacer; finally, carrying out rapid thermal processing and RCA cleaning once again to form a second titanium silicide layer. The overall thickness of titanium silicide is depending on the requiring resistance of titanium silicide under a certain line width.

Abstract translation: 通过本发明公开了一种形成具有降低的薄层电阻的窄线宽度硅化物的方法。 该方法包括：首先提供半导体衬底，其中至少形成源极/漏极区域和栅极区域，以及形成在栅极区域的侧壁上的间隔物; 然后沉积覆盖半导体衬底的钛金属层和所得结构; 接下来，进行快速热处理和RCA清洗以形成第一硅化钛层; 从而在第一钛硅化物层上形成选择性多晶硅层; 并且在所述选择性多晶硅层上沉积第二钛金属层并且覆盖所述间隔物的暴露表面; 最后进行快速热处理和RCA清洗再次形成第二硅化钛层。 硅化钛的总厚度取决于一定线宽度下硅化钛的要求电阻。

公开(公告)号：US6077784A

公开(公告)日：2000-06-20

申请号：US132876

申请日：1998-08-11

Applicant: Kun-Lin Wu ,  Meng-Jin Tsai

Inventor： Kun-Lin Wu ,  Meng-Jin Tsai

IPC: H01L21/3105 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L21/302

CPC classification number: H01L21/76829 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/3185 ,  H01L21/7684

Abstract: A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 .ANG. can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH.sub.4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH.sub.2 Cl.sub.2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second metallic line that couples electrically with the first metallic line through the via opening is formed.

Abstract translation: 用于形成金属互连的化学机械抛光工艺包括以下步骤：提供其上具有第一金属线的半导体衬底，然后在衬底和第一金属线上形成电介质层。 接下来，使用化学 - 机械抛光方法来抛光电介质层的表面。 此后，在抛光的介电层上形成薄盖层。 具有1000-3000厚度的薄盖层可以是例如二氧化硅层，磷硅酸盐玻璃层或富硅氧化物层。 形成盖层的方法包括使用硅烷（SiH4）或四乙基原硅酸盐（TEOS）作为主要反应剂的化学气相沉积法沉积氧化硅。 或者，可以通过使用化学气相沉积法以硅烷或二氯硅酸氢钠（SiH 2 Cl 2）作为主要反应剂沉积氮化硅来形成覆盖层。 最后，形成通过介电层和盖层的通路开口，并且形成通过通路孔与第一金属线电连接的第二金属线。