公开(公告)号：US20140019705A1

公开(公告)日：2014-01-16

申请号：US14027858

申请日：2013-09-16

Applicant: MOSAID Technologies Incorporated

Inventor： Hong Beom PYEON ,  Jin-Ki KIM ,  Peter B. GILLINGHAM

IPC: G06F12/02

CPC classification number: G06F12/0238 ,  G06F3/0634 ,  G06F12/04 ,  G06F12/0646 ,  G06F13/36 ,  G06F13/4234 ,  G06F13/4291 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1087

Abstract: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks.

Abstract translation: 一种复合存储器件，包括分立存储器件和用于控制分立存储器件的桥接器件。 桥接器件具有组织为存储体的存储器，其中每个存储体被配置为具有小于页面缓冲器的最大物理大小的虚拟页面大小。 因此，只有与存储在页面缓冲器中的虚拟页大小相对应的数据段被传送到存储体。 以具有有序结构的虚拟页面大小（VPS）配置命令提供虚拟页面大小，其中在命令中包含VPS配置代码的VPS数据字段的位置对应于从最不重要的银行排序到不同的银行， 最重要的银行。 VPS配置命令的大小是可变的，并且只包括配置的最高有效存储库的VPS配置代码和较低的重要库。

公开(公告)号：US20140016652A1

公开(公告)日：2014-01-16

申请号：US14030194

申请日：2013-09-18

Applicant: MOSAID Technologies Incorporated

Inventor： Abdelhakim HAFID ,  Narayanan NATARAJAN ,  Shrirang GADGIL

IPC: H04L5/00

CPC classification number: H04L5/0064 ,  H04L41/0654 ,  H04L41/0896 ,  H04L41/12 ,  H04L45/00 ,  H04L45/22 ,  H04L45/24 ,  H04L45/28 ,  H04L45/302 ,  H04L45/50 ,  H04L47/15 ,  H04L47/2408 ,  H04L47/70 ,  H04L47/746 ,  H04L47/762 ,  H04L47/781 ,  H04L47/822 ,  H04L47/825 ,  H04L47/829

Abstract: At least one substitute path is provided in place of a plurality of existing paths of a network to reallocate traffic carried by the plurality of existing paths. The total bandwidth needed to carry the traffic of the plurality of existing paths is determined. A proposed route is generated from the available links in the network. A portion of the bandwidth of a proposed route may be allocated to the needed bandwidth when the bandwidth of a proposed route is greater than or equal to the needed bandwidth. When the bandwidth of the proposed route is less than the needed bandwidth, at least one further route is generated, and the needed bandwidth is divided among the proposed route and the at least one further route such that a minimum number of further routes are generated.

Abstract translation: 提供至少一个替代路径来代替网络的多个现有路径以重新分配由多个现有路径携带的业务。 确定承载多个现有路径的业务所需的总带宽。 所提出的路由是从网络中的可用链路生成的。 当所提出的路由的带宽大于或等于所需带宽时，所提出的路由的一部分带宽可以被分配给所需的带宽。 当所提出的路由的带宽小于所需的带宽时，生成至少一个另外的路由，并且在所提出的路由和所述至少一个另外的路由之间划分所需的带宽，使得生成最小数量的其他路由。

公开(公告)号：US20130336063A1

公开(公告)日：2013-12-19

申请号：US13969184

申请日：2013-08-16

Applicant: MOSAID Technologies Incorporated

Inventor： Jin-Ki Kim

IPC: G11C16/04

CPC classification number: G11C16/04 ,  G11C7/20 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/344 ,  G11C16/3445

Abstract: In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A substrate voltage is applied to the substrate of the selected block. A common select voltage may be applied to each selected wordline and the common unselect voltage may be applied to each unselected wordline. Select and unselect voltages may be applied to any of the wordlines of a select block. A page erase verify operation may be applied to a block having plural erased pages and plural nonerased pages.

Abstract translation: 在非易失性存储器中，少于一个完整的块可能会被擦除为一个或多个页面。 通过通过晶体管将选择电压施加到多个选定字线中的每一个，并且通过传输晶体管将未选择的电压施加到所选块的多个未选择字线中的每一个。 将衬底电压施加到所选块的衬底。 可以将公共选择电压施加到每个所选择的字线，并且可以将公共未选择电压施加到每个未选择的字线。 选择和取消选择电压可以应用于选择块的任何字线。 页面擦除验证操作可以应用于具有多个擦除页面和多个非寻址页面的块。

公开(公告)号：US20130315048A1

公开(公告)日：2013-11-28

申请号：US13956933

申请日：2013-08-01

Applicant: MOSAID Technologies Incorporated

Inventor： Yehuda BINDER

IPC: H04L5/20

CPC classification number: H04L5/20 ,  H04B3/542 ,  H04L12/66 ,  H04L2012/6421 ,  H04L2012/6424 ,  H04L2012/644 ,  H04M11/062 ,  H04M11/066 ,  Y10S439/95 ,  Y10T307/297

Abstract: A device for enabling a local area network wiring structure to simultaneously carry digital data and analog telephone signals on the same transmission medium. It is particularly applicable to a network in star topology, in which remote data units (e.g. personal computers) are each connected to a hub through a cable comprising at least two pairs of conductors, providing a data communication path in each direction. Modules at each end of the cable provide a phantom path for telephony (voice band) signals between a telephone near the data set and a PBX, through both conductor pairs in a phantom circuit arrangement. All such communication paths function simultaneously and without mutual interference. The modules comprise simple and inexpensive passive circuit components.

Abstract translation: 一种用于使局域网布线结构能够在相同传输介质上携带数字数据和模拟电话信号的装置。 特别适用于星型拓扑网络，其中远程数据单元（例如，个人计算机）各自通过包括至少两对导体的电缆连接到集线器，从而在每个方向上提供数据通信路径。 电缆每端的模块通过虚拟电路布置中的两个导体对提供了数据集附近的电话和PBX之间的电话（语音频带）信号的幻像路径。 所有这些通信路径同时工作，没有相互干扰。 这些模块包括简单而廉价的无源电路组件。

公开(公告)号：US20130265839A1

公开(公告)日：2013-10-10

申请号：US13912650

申请日：2013-06-07

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Byoung Jin CHOI

IPC: G11C7/12 ,  G11C7/06

CPC classification number: G11C7/12 ,  G11C7/06 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2211/4065

Abstract: A semiconductor memory device, including: a memory cell connected to a first bitline and associated with a second bitline; a sense amplifier, including a first input/output node and a second input/output node; and an isolator connected to the bitlines and to the input/output nodes, the isolator being configured to carry out bitline isolation during a refresh operation of the memory cell, where the bitline isolation includes electrically disconnecting the first bitline from the first input/output node and electrically disconnecting the second bitline from the second input/output node, followed by: electrically re-connecting the first bitline to the first input/output node while the second bitline remains electrically disconnected from the second input/output node.

Abstract translation: 一种半导体存储器件，包括：连接到第一位线并与第二位线相关联的存储器单元; 读出放大器，包括第一输入/输出节点和第二输入/输出节点; 以及连接到所述位线和所述输入/输出节点的隔离器，所述隔离器被配置为在所述存储器单元的刷新操作期间执行位线隔离，其中所述位线隔离包括将所述第一位线与所述第一输入/输出节点电断开 并且将所述第二位线与所述第二输入/输出节点电断开，其后是：将所述第一位线电连接到所述第一输入/输出节点，同时所述第二位线与所述第二输入/输出节点电连接断开。

公开(公告)号：US20130232393A1

公开(公告)日：2013-09-05

申请号：US13865514

申请日：2013-04-18

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Steven PRZYBYLSKI

IPC: G11C29/00

CPC classification number: G11C29/00 ,  G06F11/1072 ,  H03M13/036 ,  H03M13/353 ,  H03M13/49

Abstract: A channel has a first and a second end. The first end of the channel is coupled to a transmitter. The channel is capable of transmitting symbols selected from a symbol set from the first end to the second end. The channel exhibits incomplete error introduction properties. A code comprises a set of code words. The elements of the set of code words are one or more code symbols long. The code symbols are members of the symbol set. The minimum modified Hamming separation between the elements of the set of code words in light of the error introduction properties of the channel is greater than the minimum Hamming distance between the elements of the set of code words. A memory device, a method of using the channel, and a method of generating the code are also described.

Abstract translation: 通道具有第一和第二端。 信道的第一端耦合到发射机。 信道能够发送从从第一端到第二端的符号集中选择的符号。 该通道显示不完整的错误引入属性。 代码包括一组代码字。 代码字集合的元素是一个或多个代码符号。 代码符号是符号集的成员。 根据信道的误差引入属性，码集集合的元素之间的最小修改汉明距离大于码集集合元素之间的最小汉明距离。 还描述了存储器件，使用该通道的方法以及生成代码的方法。

公开(公告)号：US20130176061A1

公开(公告)日：2013-07-11

申请号：US13718783

申请日：2012-12-18

Applicant: MOSAID Technologies Incorporated

Inventor： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

IPC: H03L7/10

CPC classification number: H03L7/08 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/095 ,  H03L7/10

Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.

Abstract translation: 延迟锁定环包括初始化电路，其确保将DLL初始化为不接近延迟与控制电压特性的任一端的工作点。 初始化电路强制DLL最初从初始延迟开始搜索锁定点，延迟在一个方向上变化，迫使DLL跳过第一个锁定点。 初始化电路仅允许DLL改变从初始延迟到达到工作点的一个方向的电压控制延迟环的延迟。

公开(公告)号：US20130169343A1

公开(公告)日：2013-07-04

申请号：US13777645

申请日：2013-02-26

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Peter GILLINGHAM

IPC: H01L21/82 ,  H03K17/00 ,  H01L21/02

CPC classification number: H01L25/0657 ,  G11C5/02 ,  G11C5/06 ,  H01L21/02697 ,  H01L21/82 ,  H01L23/481 ,  H01L23/5286 ,  H01L23/544 ,  H01L24/03 ,  H01L24/16 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/14 ,  H03K17/00 ,  H01L2924/00

Abstract: In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.

Abstract translation: 在适用于互连IC堆叠的集成电路（IC）中，除了不间断的TSV之外，还提供了中断的通硅通孔（TSV）。 中断的TSV提供除了堆栈的IC之间的公共并行路径之外的信号路径。 这允许使用TSV实现IC识别方案和其他功能，而不需要堆叠的替代IC的角旋转。

公开(公告)号：US20130121096A1

公开(公告)日：2013-05-16

申请号：US13732791

申请日：2013-01-02

Applicant: MOSAID Technologies Incorporated

Inventor： Richard C. Foss ,  Peter B. Gillingham ,  Graham Allan

IPC: G11C7/22

CPC classification number: G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03L7/0814

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Abstract translation: 用于同步存储器的时钟施加电路包括用于接收时钟输入信号的时钟输入，连接到用于接收驱动时钟信号的同步存储器的装置和用于接收用于传送时钟驱动的时钟输入信号的抽头延迟线 与时钟输入信号同步但延迟到同步存储器，延迟是时钟输入信号的时钟周期的一小部分。

公开(公告)号：US20130067118A1

公开(公告)日：2013-03-14

申请号：US13671248

申请日：2012-11-07

Applicant: Mosaid Technologies Incorporated

Inventor： Hong Beom PYEON ,  HakJune OH ,  Jin-Ki KIM ,  Shuji SUMI

IPC: G06F13/14

CPC classification number: G06F13/4243

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID accompanying the fed DT for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device.

Abstract translation: 多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND-，NOR-和AND-型闪存）被串联连接。 每个设备都有其设备类型的设备类型信息。 作为分组的串行输入（SI）中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。 设备确定馈送的DT是否匹配设备的DT。 在匹配的情况下，包括在设备中的计算器执行计算以生成伴随用于另一设备的馈送DT的ID，并且将馈送的ID锁存在设备的寄存器中。 在不匹配的情况下，跳过ID生成，并且不为另一设备生成ID。 根据设备类型匹配确定，DT与所生成或接收的ID组合。 组合的DT和ID作为传送到下一个设备的分组。 在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。 参考提供给互连设备的设备类型，依次生成ID。 将包含DT，ID和ID生成命令的SI以分组的形式发送到下一个设备。