公开(公告)号：US06562725B2

公开(公告)日：2003-05-13

申请号：US09899420

申请日：2001-07-05

申请人： Ming-Hsing Tsai ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Ming-Hsing Tsai ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L2100

CPC分类号： H01L21/76829 ,  H01L21/31116 ,  H01L21/314 ,  H01L21/7681 ,  H01L21/76834

摘要： Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed a first etch stop layer formed of a first material and a second etch stop layer formed of a second material. One of the first material and the second material is a non-nitrogenated silicon carbide material and the other of the first material and the second material is a nitrogenated silicon carbide material. By employing the first material and the second material, there may be etched completely through the first etch stop layer to reach a contact region formed there beneath while not etching completely through the second etch stop layer to reach a first dielectric layer formed there beneath.

摘要翻译： 在用于在微电子制造中形成双镶嵌孔的双镶嵌方法中，采用由第一材料形成的第一蚀刻停止层和由第二材料形成的第二蚀刻停止层。 第一材料和第二材料之一是非氮化碳化硅材料，第一材料和第二材料中的另一种是氮化碳化硅材料。 通过使用第一材料和第二材料，可以完全蚀刻通过第一蚀刻停止层以到达其下方形成的接触区域，而不完全蚀刻通过第二蚀刻停止层，以到达在其下方形成的第一介电层。

公开(公告)号：US06479389B1

公开(公告)日：2002-11-12

申请号：US09412632

申请日：1999-10-04

申请人： Ming-Hsing Tsai ,  Sheng Hsiang Chen

发明人： Ming-Hsing Tsai ,  Sheng Hsiang Chen

IPC分类号： H01L21302

CPC分类号： H01L21/76877 ,  H01L21/76886

摘要： This invention describes two new methods to form copper alloy films. In the first embodiment of this invention physical vapor deposition (PVD) or sputtering of a copper alloy film, is then followed by a chemical vapor deposition (CVD) or electro-chemical deposition (ECD) of a layer of pure copper. In the second embodiment of this invention chemical vapor deposition (CVD) or electro-chemical deposition (ECD) deposits a layer of pure copper, which is then followed by physical vapor deposition (PVD) or sputtering of a copper alloy film. In yet another embodiment to these methods, special, separate low temperature annealing steps follow said methods to enhance copper alloy formation. By the two deposition techniques briefly described above, high aspect ratio vias and trenches can be filled with copper corrosion and electromigration resistant alloys.

摘要翻译： 本发明描述了形成铜合金膜的两种新方法。 在本发明的第一实施例中，铜合金膜的物理气相沉积（PVD）或溅射之后是纯铜层的化学气相沉积（CVD）或电化学沉积（ECD）。 在本发明的第二实施例中，化学气相沉积（CVD）或电化学沉积（ECD）沉积一层纯铜，然后进行物理气相沉积（PVD）或铜合金膜的溅射。 在这些方法的另一个实施方案中，特殊的分开的低温退火步骤遵循所述方法以增强铜合金的形成。 通过上述两种沉积技术，可以用铜腐蚀和电迁移合金填充高纵横比通孔和沟槽。

公开(公告)号：US06420258B1

公开(公告)日：2002-07-16

申请号：US09434564

申请日：1999-11-12

申请人： Sheng Hsiung Chen ,  Ming-Hsing Tsai

发明人： Sheng Hsiung Chen ,  Ming-Hsing Tsai

IPC分类号： H01L214763

CPC分类号： H01L21/76879

摘要： A novel and improved method of fabricating an integrated circuit, in which special copper films are formed by a combination of physical vapor deposition (PVD), chemical mechanical polish (CMP) and electrochemical copper deposition (ECD) techniques. The methods of the present invention make efficient use of several process steps resulting in less processing time, lower costs and higher device reliability. By these techniques, high aspect ratio trenches can be filled with copper without the problem of dishing. A special, selective electrochemical deposition (ECD) of copper metal is utilized taking place only on the seed layer in the trench. This auto-plating or “plate-up” occurs only in the trench and provides good sealing around the trench perimeter and fine copper metal coverage of the trench for subsequent robust interconnects. The selective plating of copper provides a robust copper film that is easily removed by subsequent chemical mechanical polish (CMP) and tends to be more uniform and free of the usual defects associated with CMP films.

摘要翻译： 一种新颖且改进的制造集成电路的方法，其中通过物理气相沉积（PVD），化学机械抛光（CMP）和电化学铜沉积（ECD）技术的组合形成特殊的铜膜。 本发明的方法有效地利用几个工艺步骤，导致更少的处理时间，更低的成本和更高的器件可靠性。 通过这些技术，可以用铜填充高纵横比沟槽，而不会出现凹陷的问题。 仅在沟槽中的种子层上使用​​铜金属的特殊的选择性电化学沉积（ECD）。 这种自动电镀或“平板化”仅发生在沟槽中，并且在沟槽周边和沟槽的细铜金属覆盖层周围提供良好的密封以用于随后的鲁棒互连。 铜的选择性电镀提供了坚固的铜膜，其易于通过后续的化学机械抛光（CMP）去除，并且趋向于更均匀并且没有与CMP膜相关的常见缺陷。

公开(公告)号：US06224737B1

公开(公告)日：2001-05-01

申请号：US09377540

申请日：1999-08-19

申请人： Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： C25D502

CPC分类号： H01L21/76877 ,  C25D3/38 ,  C25D5/48 ,  C25D7/123 ,  H01L21/2885 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure having a trench formed therein is provided. The semiconductor structure may be a substrate with an overlying interlevel metal dielectric layer having the trench. A voltage is applied to the trenched semiconductor inducing a bias field where there is a first field proximate the trench bottom and a second field, greater than the first field, proximate the trench's upper side walls and the semiconductor upper surface proximate the trench. The semiconductor structure is placed into an electroplating solution containing a predetermined concentration of brighteners and levelers. Because of the induced bias field, the brightener concentration is greater proximate the trench bottom and the leveler concentration is greater the trench's upper side walls and the semiconductor upper surface proximate the trench. A copper layer having a predetermined thickness is then electrolytically deposited within the trench in a “bottom-up” fashion and blanket fills the upper surface of the semiconductor structure. The structure may then be planarized by CMP to create a planarized copper filled trench.

摘要翻译： 提供具有形成在其中的沟槽的半导体结构。 半导体结构可以是具有具有沟槽的上覆层间金属介电层的衬底。 电压被施加到沟槽半导体，其诱导偏置场，其中存在靠近沟槽底部的第一场和大于第一场，接近沟槽的上侧壁和靠近沟槽的半导体上表面的第二场。 将半导体结构放入含有预定浓度的增白剂和矫直剂的电镀溶液中。 由于感应偏压场，光滑剂浓度在沟槽底部附近较大，并且矫直剂浓度大于沟槽的上侧壁和接近沟槽的半导体上表面。 然后将具有预定厚度的铜层以“自下而上”的方式电解沉积在沟槽内，并且覆盖填充半导体结构的上表面。 然后可以通过CMP平面化该结构以产生平坦化的铜填充沟槽。

公开(公告)号：US6133144A

公开(公告)日：2000-10-17

申请号：US368864

申请日：1999-08-06

申请人： Ming-Hsing Tsai ,  Shau-Lin Shue

发明人： Ming-Hsing Tsai ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/7681

摘要： An improved and novel process for fabricating unique interconnect conducting lines and via contact structures has been developed. Using this special self aligned dual damascene process, special interconnect conducting lines and via contacts are formed which have low parasitic capacitance (low RC time constants). The invention incorporates the use of double etch stop or etch barrier layers. The key process step of this invention is special patterning of the etch stop or etch barrier layer. This is the advantage of this invention over Prior Art processes that need a continuous, thick stop layer that has a etching selectivity to silicon dioxide, SiO.sub.2 (increasing parasitic capacitance). However, in this invention a self aligned dual damascene process and structure is presented that is easier to process and has low parasitic capacitance. Repeating the self aligned dual damascene processing steps, constructs multilevel conducting structures. This process reduces processing time, reduces the cost of ownership, (compatible with low dielectric constant materials) and at the same time produces a product with superior lines and via contact structures (by use of special etch stop or etch barrier layer patterning), hence improving reliability.

摘要翻译： 已经开发了用于制造独特的互连导线和通孔接触结构的改进和新颖的工艺。 使用这种特殊的自对准双镶嵌工艺，形成了具有低寄生电容（低RC时间常数）的特殊互连导线和通孔触点。 本发明包括使用双蚀刻停止层或蚀刻阻挡层。 本发明的关键工艺步骤是蚀刻停止或蚀刻阻挡层的特殊图案化。 这是本发明优于现有技术方法的优点，其需要具有对二氧化硅，SiO 2（增加寄生电容）的蚀刻选择性的连续的厚的停止层。 然而，在本发明中，提出了一种易于处理并具有低寄生电容的自对准双镶嵌工艺和结构。 重复自对准双镶嵌加工步骤，构建多层导电结构。 这个过程减少了处理时间，降低了所有权成本（与低介电常数材料兼容），同时产生了具有优异线条和通孔接触结构的产品（通过使用特殊的蚀刻阻挡层或蚀刻阻挡层图案），因此 提高可靠性。

公开(公告)号：US07638859B2

公开(公告)日：2009-12-29

申请号：US11144742

申请日：2005-06-06

申请人： Yung-Cheng Lu ,  Ming-Hsing Tsai

发明人： Yung-Cheng Lu ,  Ming-Hsing Tsai

IPC分类号： H01L23/58 ,  H01L23/52

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnects with harmonized stress and methods for fabricating the same. An interconnect comprises a substrate having a conductive member. A composite low-k dielectric layer interposed with at least one stress-harmonizing layer therein overlies the substrate. A conductive feature in the composite low-k dielectric layer passes through the at least one stress-harmonizing layer to electrically connect the conductive member.

摘要翻译： 具有协调应力的互连和制造它的方法。 互连件包括具有导电部件的基板。 插入其中的至少一个应力协调层的复合低k电介质层覆盖在基板上。 复合低k电介质层中的导电特征通过至少一个应力协调层以电连接导电构件。

公开(公告)号：US07226860B2

公开(公告)日：2007-06-05

申请号：US10833154

申请日：2004-04-28

申请人： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

发明人： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

IPC分类号： H01L21/44

CPC分类号： H01L21/2885 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76877

摘要： A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle θ less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.

公开(公告)号：US20070052096A1

公开(公告)日：2007-03-08

申请号：US11210226

申请日：2005-08-23

申请人： Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai

发明人： Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai

IPC分类号： H01L21/4763

CPC分类号： H01L23/528 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer comprises metal ions.

摘要翻译： 提供了可以减少或甚至防止对其中低k电介质层的损坏的用于形成其的半导体器件及其制造方法。 提供了一种半导体器件，包括衬底。 其中具有至少一个导电特征的电介质层覆盖在衬底上。 绝缘覆盖层覆盖邻近导电特征的低k电介质层的顶表面，其中绝缘帽层包括金属离子。

公开(公告)号：US07169700B2

公开(公告)日：2007-01-30

申请号：US10913759

申请日：2004-08-06

申请人： Chung Liang Chang ,  Ming Hsing Tsai ,  Winston Sue

发明人： Chung Liang Chang ,  Ming Hsing Tsai ,  Winston Sue

IPC分类号： H01L21/4763

CPC分类号： H01L21/76877 ,  C25D5/18 ,  C25D7/123 ,  H01L21/2885

摘要： A metal filled damascene structure with improved electromigration resistance and method for forming the same, the method including providing a semiconductor process wafer comprising damascene openings; and, depositing metal and at least one metal dopant according to an ECD process to from a metal filled damascene comprising a doped metal alloy portion.

摘要翻译： 一种具有改进的电迁移电阻的金属填充镶嵌结构及其形成方法，所述方法包括提供包括镶嵌开口的半导体工艺晶片; 以及根据ECD工艺将金属和至少一种金属掺杂剂沉积到包含掺杂金属合金部分的金属填充镶嵌件中。

公开(公告)号：US20060243596A1

公开(公告)日：2006-11-02

申请号：US11119183

申请日：2005-04-28

申请人： Ming-Wei Lin ,  Ming-Hsing Tsai

发明人： Ming-Wei Lin ,  Ming-Hsing Tsai

IPC分类号： C25D7/12 ,  C25D17/06

CPC分类号： C25D17/06 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/005 ,  H01L21/2885

摘要： An electrochemical plating apparatus and method for facilitating uniform current distribution across a wafer during loading into an ECP (electrochemical plating) apparatus is disclosed. The apparatus includes a bath container for containing a bath solution, an anode provided in the bath container, a cathode ring for supporting a wafer in the bath container and a current source electrically connected to the anode and the cathode ring. According to the method, a voltage potential is applied to the cathode ring as it is immersed into the solution and prior to immersion of the wafer in the solution, thereby facilitating a substantially uniform plating current across the wafer upon immersion of the wafer.