公开(公告)号：US06573147B2

公开(公告)日：2003-06-03

申请号：US10055260

申请日：2001-10-26

Applicant: Kwang-jin Moon ,  Hee-sook Park ,  Myoung-bum Lee

Inventor： Kwang-jin Moon ,  Hee-sook Park ,  Myoung-bum Lee

IPC: H01L21331

CPC classification number: H01L21/76829 ,  H01L21/32051

Abstract: A semiconductor device having a contact using a crack-protecting layer and a method of forming the same are provided. The crack-protecting layer formed of a dielectric material is formed on an interlayer dielectric layer. The crack-protecting layer relieves or absorbs residual stress generated on a conductive layer used in forming a contact plug. Thus, a contact can be formed without damage to the interlayer dielectric layer due to residual stress.

Abstract translation: 提供具有使用裂纹保护层的接触的半导体器件及其形成方法。 由介电材料形成的裂纹保护层形成在层间电介质层上。 裂纹保护层减轻或吸收在用于形成接触插塞的导电层上产生的残余应力。 因此，可以形成接触，而不会由于残余应力而损坏层间电介质层。

公开(公告)号：US5742472A

公开(公告)日：1998-04-21

申请号：US674883

申请日：1996-07-03

Applicant: Myoung-bum Lee ,  Hyeon-deok Lee

Inventor： Myoung-bum Lee ,  Hyeon-deok Lee

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01G4/06

CPC classification number: H01L27/10852 ,  H01L28/40

Abstract: A method for fabricating a capacitor on a substrate includes the steps of forming an insulating layer on the substrate, and forming the first plate electrode on the insulating layer. A first dielectric layer is then formed on the plate electrode, and a first common storage electrode is formed on the first dielectric layer. A contact hole is then formed through the insulating layer, the first plate electrode, the first dielectric layer, and the first common storage electrode, thereby exposing a predetermined portion of the substrate. A first spacer is formed on a sidewall of the contact hole, and a conductive plug is formed in the contact hole extending from the substrate to the first common storage electrode.

Abstract translation: 在基板上制造电容器的方法包括以下步骤：在基板上形成绝缘层，并在绝缘层上形成第一平板电极。 然后在平板电极上形成第一电介质层，在第一电介质层上形成第一公共存储电极。 然后通过绝缘层，第一平板电极，第一介电层和第一公共存储电极形成接触孔，从而暴露基板的预定部分。 第一间隔件形成在接触孔的侧壁上，并且在从基板延伸到第一公共存储电极的接触孔中形成导电插塞。

公开(公告)号：US08916922B2

公开(公告)日：2014-12-23

申请号：US13724187

申请日：2012-12-21

Applicant: Kyung-Tae Jang ,  Myoung-Bum Lee ,  Ji-Youn Seo ,  Chang-Won Lee ,  Yong-Chae Jung ,  Woong-Hee Sohn

Inventor： Kyung-Tae Jang ,  Myoung-Bum Lee ,  Ji-Youn Seo ,  Chang-Won Lee ,  Yong-Chae Jung ,  Woong-Hee Sohn

IPC: H01L29/792 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.

Abstract translation: 半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体 层在垂直方向。 这些部分中的至少一些是相邻的多个通道的相应通道。 每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极 或填充层图案。

公开(公告)号：US20120007165A1

公开(公告)日：2012-01-12

申请号：US13181281

申请日：2011-07-12

Applicant: Myoung-Bum LEE ,  Jae-Hwang SIM ,  In-Sun PARK ,  Jin-Gi HONG ,  Ju-Seon GOO ,  Seung-Bae PARK ,  Seung-Yup LEE ,  Du-Heon SONG ,  Jeong-Dong CHOE ,  Seok-Won LEE

Inventor： Myoung-Bum LEE ,  Jae-Hwang SIM ,  In-Sun PARK ,  Jin-Gi HONG ,  Ju-Seon GOO ,  Seung-Bae PARK ,  Seung-Yup LEE ,  Du-Heon SONG ,  Jeong-Dong CHOE ,  Seok-Won LEE

IPC: H01L29/788 ,  H01L27/088

CPC classification number: H01L29/7881 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device includes a substrate, a plurality of gate structures, a first insulating interlayer pattern, and a second insulation layer pattern. The substrate has an active region and a field region, each of the active region and the field region extends in a first direction, and the active region and the field region are alternately and repeatedly arranged in a second direction substantially perpendicular to the first direction. The gate structures are spaced apart from each other in the first direction, each of the gate structures extends in the second direction. The first insulation layer pattern is formed on a portion of a sidewall of each gate structure. The second insulation layer pattern covers the gate structures and the first insulation layer pattern, and has an air tunnel between the gate structures, the air tunnel extending in the second direction.

Abstract translation: 半导体器件包括衬底，多个栅极结构，第一绝缘层间图案和第二绝缘层图案。 基板具有有源区域和场区域，有源区域和场区域中的每一个沿着第一方向延伸，并且有源区域和场区域在基本上垂直于第一方向的第二方向上交替地和重复地布置。 栅极结构在第一方向上彼此间隔开，每个栅极结构沿第二方向延伸。 第一绝缘层图案形成在每个栅极结构的侧壁的一部分上。 第二绝缘层图案覆盖栅极结构和第一绝缘层图案，并且在栅极结构之间具有沿第二方向延伸的空气通道的空气通道。

公开(公告)号：US07723755B2

公开(公告)日：2010-05-25

申请号：US12003973

申请日：2008-01-04

Applicant: Si-hyung Lee ,  Sang-ryol Yang ,  Myoung-bum Lee ,  Ki-hyun Hwang

Inventor： Si-hyung Lee ,  Sang-ryol Yang ,  Myoung-bum Lee ,  Ki-hyun Hwang

IPC: H01L27/00

CPC classification number: H01L27/10876 ,  H01L27/10891

Abstract: Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce the height of the semiconductor device and to reduce the degradation of the oxide layer caused by chlorine ions from the application of a TiN metal gate, and a method of fabricating the semiconductor device. The semiconductor device may comprise a semiconductor substrate defined by a device isolation layer and comprising an active region including a trench and one or more recess channels, a gate isolation layer on the surface of the trench, a gate electrode layer on the surface of the gate isolation layer, and a word line by which the trench may be buried on the surface of the gate electrode layer.

Abstract translation: 提供一种具有掩埋字线结构的半导体器件，其中栅极电极和字线可以被掩埋在衬底内以降低半导体器件的高度并且减少由来自应用的氯离子引起的氧化物层的劣化 的TiN金属栅极，以及制造半导体器件的方法。 半导体器件可以包括由器件隔离层限定的半导体衬底，并且包括有源区，包括沟槽和一个或多个凹陷通道，沟槽表面上的栅极隔离层，栅极表面上的栅极电极层 隔离层以及沟槽可以埋在栅电极层的表面上的字线。

公开(公告)号：US20090321810A1

公开(公告)日：2009-12-31

申请号：US12476574

申请日：2009-06-02

Applicant: Min-Kyung RYU ,  Byong-sun JU ,  Myoung-bum LEE ,  Seung-hyun LIM ,  Sung-hae LEE ,  Young-sun KIM

Inventor： Min-Kyung RYU ,  Byong-sun JU ,  Myoung-bum LEE ,  Seung-hyun LIM ,  Sung-hae LEE ,  Young-sun KIM

IPC: H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L27/11519 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/513

Abstract: Provided is a non-volatile memory device including; a substrate having source/drain regions and a channel region between the source/drain regions; a tunneling insulating layer formed in the channel region of the substrate; a charge storage layer formed on the tunneling insulating layer; a blocking insulating layer formed on the charge storage layer, and comprising a silicon oxide layer and a high-k dielectric layer sequentially formed; and a control gate formed on the blocking insulating layer, wherein an equivalent oxide thickness of the silicon oxide layer is equal to or greater than that of the high-k dielectric layer.

Abstract translation: 提供了一种非易失性存储器件，包括： 具有源极/漏极区域和源极/漏极区域之间的沟道区域的衬底; 形成在所述基板的沟道区域中的隧道绝缘层; 形成在隧道绝缘层上的电荷存储层; 形成在所述电荷存储层上的阻挡绝缘层，并且依次形成氧化硅层和高k电介质层; 以及形成在所述阻挡绝缘层上的控制栅极，其中所述氧化硅层的等效氧化物厚度等于或大于所述高k电介质层的氧化物厚度。

公开(公告)号：US20090159955A1

公开(公告)日：2009-06-25

申请号：US12235689

申请日：2008-09-23

Applicant: Sung-hae LEE ,  Ki-yeon PARK ,  Min-Kyung RYU ,  Myoung-bum LEE ,  Jun-noh LEE

Inventor： Sung-hae LEE ,  Ki-yeon PARK ,  Min-Kyung RYU ,  Myoung-bum LEE ,  Jun-noh LEE

IPC: H01L29/788 ,  H01L29/792

CPC classification number: H01L29/42324 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

Abstract: A nonvolatile memory device includes a semiconductor substrate, a tunneling insulation layer on the semiconductor substrate, a charge storage layer on the tunneling insulation layer, an inter-electrode insulation layer on the charge storage layer, and a control gate electrode on the inter-electrode insulation layer. The inter-electrode insulation layer includes a high-k dielectric layer having a dielectric constant greater than that of a silicon nitride, and an interfacial layer between the charge storage layer and the high-k dielectric layer. The interfacial layer includes a silicon oxynitride layer.

Abstract translation: 非易失性存储器件包括半导体衬底，半导体衬底上的隧道绝缘层，隧道绝缘层上的电荷存储层，电荷存储层上的电极间绝缘层和电极上的控制栅电极 绝缘层。 电极间绝缘层包括具有大于氮化硅的介电常数的高k电介质层，以及电荷存储层和高k电介质层之间的界面层。 界面层包括氧氮化硅层。

公开(公告)号：US20090124070A1

公开(公告)日：2009-05-14

申请号：US12270014

申请日：2008-11-13

Applicant: Dong Chul Yoo ,  Myoung-bum Lee ,  Young-geun Park ,  Han-mei Choi ,  Se-hoon Oh ,  Byong-ju Kim ,  Kyong-won An ,  Seon-ho Jo

Inventor： Dong Chul Yoo ,  Myoung-bum Lee ,  Young-geun Park ,  Han-mei Choi ,  Se-hoon Oh ,  Byong-ju Kim ,  Kyong-won An ,  Seon-ho Jo

IPC: H01L21/3205

CPC classification number: H01L21/31616 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/3145 ,  H01L21/31604

Abstract: Methods of manufacturing a semiconductor device are provided including forming a charge storage layer on a gate insulating layer that is on a semiconductor substrate. A blocking insulating layer is formed on the charge storage layer and an electrode layer is formed on the blocking insulating layer. The blocking insulating layer may be formed by forming a lower metal oxide layer at a first temperature and forming an upper metal oxide layer on the lower metal oxide layer at a second temperature, lower than the first temperature.

Abstract translation: 提供了制造半导体器件的方法，包括在半导体衬底上的栅极绝缘层上形成电荷存储层。 在电荷存储层上形成阻挡绝缘层，在隔离绝缘层上形成电极层。 阻挡绝缘层可以通过在第一温度下形成下部金属氧化物层并在低于第一温度的第二温度下在下部金属氧化物层上形成上部金属氧化物层而形成。

公开(公告)号：US20080032512A1

公开(公告)日：2008-02-07

申请号：US11828541

申请日：2007-07-26

Applicant: Dong-Chan KIM ,  Seong-Hoon JEONG ,  Myoung-Bum LEE ,  Sang-Bom KANG ,  Jin-Hwa HEO

Inventor： Dong-Chan KIM ,  Seong-Hoon JEONG ,  Myoung-Bum LEE ,  Sang-Bom KANG ,  Jin-Hwa HEO

IPC: H01L21/31

CPC classification number: H01L21/0214 ,  H01L21/02252 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/518 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device in a process camber is disclosed. The method includes forming a preliminary dielectric layer including oxynitride on a substrate by performing a plasma oxidation treatment and a first plasma nitridation treatment, wherein the preliminary dielectric layer has a substantially uniform nitrogen concentration profile to a defined depth, and forming a dielectric layer from the preliminary dielectric layer by performing a second plasma nitridation treatment, wherein the nitrogen concentration of the dielectric layer is higher than that of the preliminary dielectric layer.

Abstract translation: 公开了一种制造半导体器件的方法。 该方法包括通过进行等离子体氧化处理和第一等离子体氮化处理在衬底上形成包括氧氮化物的预备电介质层，其中预备电介质层具有基本上均匀的氮浓度分布到规定的深度，并且从 通过进行第二等离子体氮化处理，其中所述电介质层的氮浓度高于所述预备介电层的氮浓度。

公开(公告)号：US06858529B2

公开(公告)日：2005-02-22

申请号：US10440777

申请日：2003-05-19

Applicant: Eun-Ae Chung ,  Myoung-Bum Lee ,  Young-Pil Kim ,  Jin-Gyun Kim ,  Bean-Jun Jin

Inventor： Eun-Ae Chung ,  Myoung-Bum Lee ,  Young-Pil Kim ,  Jin-Gyun Kim ,  Bean-Jun Jin

IPC: H01L21/28 ,  H01L21/225 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L21/4763

CPC classification number: H01L21/76877 ,  H01L21/2257 ,  H01L21/28525 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug can be formed in the contact hole wherein at least a portion of the polysilicon contact plug is doped with an element having a diffusion coeffient that is less than a diffusion coefficient of phosphorus (P). Related structures are also discussed.

Abstract translation: 形成半导体器件可以包括在包括其导电区域的半导体衬底上形成绝缘层，其中绝缘层具有暴露导电区域的一部分的接触孔。 可以在接触孔中形成多晶硅接触插塞，其中多晶硅接触插塞的至少一部分掺杂有具有小于磷（P）的扩散系数的扩散系数的元件。 还讨论了相关结构。